Lars Bååth from Onsala has suggested that perhaps it would be sensible to replace the whole data buffer with a new design, perhaps with a PC expansion card:
Dear Ari,It seems to me that it may be better and easier for us to redesign the data buffer than to try to find out what the "S1883" UART chip is designed to do or not do. It should be straight forward to design a new and modern data buffer. Maybe using modern and commercially available PC-cards?
Cheers,
Lars
I replied him with the following message:
Hi Lars,Well, in principle yes and in practice perhaps yes. The functional essence of the data buffer is really very minimalistic:
- Take the input signals of:
- tape data (from decoder)
- tape clock (from decoder, as well)
- frame sync (decoder detects this, too)
- Turn serial data into words that...
- ...can be stuffed into a memory buffer.
Functions 1+2) would require a couple of shift registers and counters. I don't know whether these are commercially available, I'd suspect that actually not. Having new shift registers would enable rates higher than 10MHz, but our data source is the old MkIII decoder---again, it would be in principle possible to replace the decoder, too, but if we use simple and straightforward hardware for a new decoder, it'll call for more and more PC software to really do all those parity error and display functions that are being done in hardware of the current MkIII decoder.
For function 3) there should be commercially available parallel input -> DMA cards. Again, relying on PC hardware would be the key to simple hardware, but the PC architecture enables only 16-bit word sized DMA channels 4--7 to write continuously, in one sweep into a buffer of max 128kB---coincidentally the same size we are having today.
Having more buffer memory or not using up the limited number of available DMA channels of a standard PC would require a design with own DRAM memory on a self-designed expansion card. I'm certain that even this wouldn't be that hard---I'm sure Jouko Ritakari could be persuaded to design this---but now the design issues would sum up to:
- having a basic PC card AT-ISA bus interface
- having input data shift registers
- having DRAM buffer
- having DRAM refresh
- having dual-ported "window" into that DRAM or some kind of "windowing" DMA support
Now I'm not any longer convinced that this would be comparable to trying an oscillator with a higher rate in place of the 5046 baud rate generator and see if the current S1883 UART can give us 12-fold increase in thruput.
If this fails, I would still prefer designing the host software that will interact with a data buffer of some kind before doing any other more involved modifications than a simple oscillator swap. I mean, we actually need to see if we really can use the "concept" of data buffer for anything useful: pcal detection, rt fringe checks et al will all be possible even with unmodified data buffer, albeit they'll be too slow to be widely useful. I can make sure in the software design that the actual data buffer hardware can be swapped beneath of the high-level software without much trouble.
Cheers,
Ari
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