The bidirectional serial interface of the data buffer is presented in Mark~III drawing ``6004-005'', found in the data buffer section of the Mark~III VLBI ``Blue Binder.'' An ``S1883'' UART chip is used to accept one-character ASCII command characters from the host computer and to transmit pure 8-bit binary responses back to host.
The UART chip is clocked with its own baud rate clock, ``BCLK'', independent of the data buffer system clock, ``UCLK'', found on page 2 of the schematics. If an ``S1883'' UART will tolerate this, it could be driven with a clock rate that results in the baud rate of 115200~baud, customarily referred to as ``115~kbaud.''
This baud rate is the maximum that the ordinary PC serial ports and
Linux serial drivers can
support. To prevent incoming characters to be lost due to missed
interrupts, a serial port with an 16550A FIFO-buffered UART is
required. The FS~PC
has such a port as ``COM2:'' and the DigiBoard ports should also
be usable as continuous parity/speed changes are not required.
The easiest way to have a new baud rate clock might be to replace the existing baud rate generator chip ``5046'' with a fixed-rate oscillator.
The new 115200 baud RS232 interface requires at least approximately (128*1024*10/115200) = 11.4~seconds to send the contents of the whole buffer over to the host computer. It may well take slightly longer due to software overhead---on the other hand, the amount of transferred data could be slightly reduced from the whole buffer contents to accommodate one transfer in the 10-second retrigger period of the data buffer.
Steps to test this option are outlined in section steps . If this fails for some reason, the parallel options presented below might be considered.
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