05.06.2009 -- v1.2

 - added commands: 'samplestats', 'agc <0|1>', 'quantizationlevel <2..126>'

   
    samplestats: at random intervals the PowerPC takes a 2-bit sample from
                 every channel, builds per-channel histograms, computes
                 per-channel power and symbol distribution

    quantizationlevel: an easier way to change the bit_levels register
                that contains the 8-bit per-channel low and high threshold 
                values that are used in the 8-bit sample to 2-bit sample conversion

    agc: config register bit 5, enables or disables the software AGC

  - added Software AGC

       the thresholds in the bit_levels register are adjusted by +-1
       every couple of seconds (when a new sample histogram is ready),
       this moves towards and around a goal 16%:*:*:16% distribution

02.06.2009 -- v1.1

 - both channels are sent over 10G
 - the UDP packet-interleaving FIFO is not included in this design,
   this means channel 1 is send over 10G port#1 and channel 2 over port #2,
   you need to connect both iBob 10G ports to your 10G switch

27.05.2009 -- v1.0

  supports ADC sample clock rates up to and over 1024 MHz

  - the derived system clock is 256 MHz
  - both iADC channels are sampled at 1024 Ms/s each
  - only the I-channel is sent over the network

  - added 8-bit=>2-bit Conversion

      signed char quantization levels are in register bit_levels
  
  - improved older vhld such that a 256 MHz IP clock does not cause timing errors

      rtc32_v14 32-bit : better counter layout, pipelining

      bitreducer8to2_v10.vhd : better sample to threshold comparisons, resamples the threshold
      bitreducer8to2wide_v10.vhd : -"-

      vdif_packetizer_v15.vhd : "dw64_count_v := dw64_count_v + 1" is replaced 
          by a dw64_count_v + 1 precomputed one cycle earlier