
-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- synopsys translate_off
library unisim;
use unisim.vcomponents.all;
-- synopsys translate_on
entity xlclockgenerator is
    generic (ensure_clks_stable       : boolean := false;
             lcm_select               : integer := 0;
             frequency_mode           : string  := "low";
             clkdv_divide_generic     : real    := 2.0;
             clkdv_divide_attribute   : string  := "2.0";
             clkfx_multiply_generic   : integer := 4;
             clkfx_multiply_attribute : string  := "4";
             clkfx_divide_generic     : integer := 1;
             clkfx_divide_attribute   : string  := "1");
    port (clk   : in std_logic;
          rst   : in std_logic;
          clk0  : out std_logic;
          clk2x : out std_logic;
          clkfx : out std_logic;
          clkdv : out std_logic;
          lock  : out std_logic);
end xlclockgenerator;
architecture structural of xlclockgenerator is
   component bufg
      port(i: in std_logic;
           o: out std_logic);
   end component;
   component bufgmux
      port(i0 : in std_logic;
           i1 : in std_logic;
           s  : in std_logic;
           o  : out std_logic);
   end component;
   component dcm
      -- synopsys translate_off
      generic (clkout_phase_shift    : string := "fixed";
               dll_frequency_mode    : string := "low";
               duty_cycle_correction : boolean := true;
               clkdv_divide          : real := 2.0;
               clkfx_multiply        : integer := 4;
               clkfx_divide          : integer := 1);
      -- synopsys translate_on
      port (clkin    : in  std_logic;
            clkfb    : in  std_logic;
            dssen    : in  std_logic;
            psincdec : in  std_logic;
            psen     : in  std_logic;
            psclk    : in  std_logic;
            rst      : in  std_logic;
            clk0     : out std_logic;
            clk90    : out std_logic;
            clk180   : out std_logic;
            clk270   : out std_logic;
            clk2x    : out std_logic;
            clk2x180 : out std_logic;
            clkdv    : out std_logic;
            clkfx    : out std_logic;
            clkfx180 : out std_logic;
            locked   : out std_logic;
            psdone   : out std_logic;
            status   : out std_logic_vector(7 downto 0));
   end component;
   attribute dll_frequency_mode    : string;
   attribute duty_cycle_correction : string;
   attribute startup_wait          : string;
   attribute clkdv_divide          : string;
   attribute clkfx_multiply        : string;
   attribute clkfx_divide          : string;
   attribute duty_cycle_correction of dcm_comp1 : label is "true";
   attribute startup_wait of dcm_comp1          : label is "false";
   attribute dll_frequency_mode of dcm_comp1    : label is frequency_mode;
   attribute clkdv_divide of dcm_comp1   : label is clkdv_divide_attribute;
   attribute clkfx_multiply of dcm_comp1 : label is clkfx_multiply_attribute;
   attribute clkfx_divide of dcm_comp1   : label is clkfx_divide_attribute;
   component fdre
      port(q  : out   std_ulogic;
           d  : in    std_ulogic;
           c  : in    std_ulogic;
           r  : in    std_ulogic;
           ce : in    std_ulogic);
   end component;
   signal feedback    : std_logic;
   signal clklcm      : std_logic;
   signal clk0unbuf   : std_logic;
   signal clk0buf     : std_logic;
   signal clk2xunbuf  : std_logic;
   signal clkfxunbuf  : std_logic;
   signal clkdvunbuf  : std_logic;
   signal clkswitch   : std_logic;
   signal intlock     : std_logic;
begin
   dcm_comp1: dcm
      -- synopsys translate_off
      generic map (dll_frequency_mode => frequency_mode,
                   clkdv_divide       => clkdv_divide_generic,
                   clkfx_multiply     => clkfx_multiply_generic,
                   clkfx_divide       => clkfx_divide_generic)
      -- synopsys translate_on
      port map (clkin    => clk,
                clkfb    => feedback,
                dssen    => '0',
                psincdec => '0',
                psen     => '0',
                psclk    => '0',
                rst      => rst,
                clk0     => clk0unbuf,
                clk2x    => clk2xunbuf,
                clkfx    => clkfxunbuf,
                clkdv    => clkdvunbuf,
                locked   => intlock);
   bufgmux_clk0: bufgmux
      port map (i0 => '0',
                i1 => clk0unbuf,
                o  => clk0buf,
                s  => clkswitch);
   bufgmux_clk2x: bufgmux
      port map (i0 => '0',
                i1 => clk2xunbuf,
                o  => clk2x,
                s  => clkswitch);
   bufgmux_clkfx: bufgmux
      port map (i0 => '0',
                i1 => clkfxunbuf,
                o  => clkfx,
                s  => clkswitch);
   bufgmux_clkdv: bufgmux
      port map (i0 => '0',
                i1 => clkdvunbuf,
                o  => clkdv,
                s  => clkswitch);
   stability_req: if (ensure_clks_stable = true) generate
      mux_ctrl_reg: fdre
         port map (d  => intlock,
                   q  => clkswitch,
                   ce => '1',
                   c  => clklcm,
                   r  => rst);
      bufg_feedback: bufg
         port map(i => clk0unbuf,
                  o => feedback);
      lcm_is_clk0: if (lcm_select = 0) generate
         clklcm <= feedback;
      end generate;
      lcm_is_clkdv: if (lcm_select = 1) generate
         bufg_lcmclk: bufg
            port map(i => clkdvunbuf,
                     o => feedback);
      end generate;
   end generate;
   stability_not_req: if (ensure_clks_stable = false) generate
      feedback  <= clk0buf;
      clkswitch <= '1';
   end generate;
   lock <= intlock;
   clk0 <= clk0buf;
end architecture structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;

entity expres4g1024m_dw is
  port (
    clk: in std_logic;
    expres4g1024m_adc_user_data_valid: in std_logic;
    expres4g1024m_adc_user_datai0: in std_logic_vector(7 downto 0);
    expres4g1024m_adc_user_datai1: in std_logic_vector(7 downto 0);
    expres4g1024m_adc_user_datai2: in std_logic_vector(7 downto 0);
    expres4g1024m_adc_user_datai3: in std_logic_vector(7 downto 0);
    expres4g1024m_adc_user_dataq0: in std_logic_vector(7 downto 0);
    expres4g1024m_adc_user_dataq1: in std_logic_vector(7 downto 0);
    expres4g1024m_adc_user_dataq2: in std_logic_vector(7 downto 0);
    expres4g1024m_adc_user_dataq3: in std_logic_vector(7 downto 0);
    expres4g1024m_adc_user_outofrangei0: in std_logic;
    expres4g1024m_adc_user_outofrangei1: in std_logic;
    expres4g1024m_adc_user_outofrangeq0: in std_logic;
    expres4g1024m_adc_user_outofrangeq1: in std_logic;
    expres4g1024m_adc_user_sync0: in std_logic;
    expres4g1024m_adc_user_sync1: in std_logic;
    expres4g1024m_adc_user_sync2: in std_logic;
    expres4g1024m_adc_user_sync3: in std_logic;
    expres4g1024m_bit_levels_user_data_out: in std_logic_vector(31 downto 0);
    expres4g1024m_config_user_data_out: in std_logic_vector(31 downto 0);
    expres4g1024m_dest_ip_user_data_out: in std_logic_vector(31 downto 0);
    expres4g1024m_dest_port_offset_user_data_out: in std_logic_vector(31 downto 0);
    expres4g1024m_dest_port_user_data_out: in std_logic_vector(31 downto 0);
    expres4g1024m_national_semi_pll_user_data_out: in std_logic_vector(31 downto 0);
    expres4g1024m_rtc_settime_user_data_out: in std_logic_vector(31 downto 0);
    expres4g1024m_rtc_starttime_user_data_out: in std_logic_vector(31 downto 0);
    expres4g1024m_rtc_stoptime_user_data_out: in std_logic_vector(31 downto 0);
    expres4g1024m_ten_gbe1_led_rx: in std_logic;
    expres4g1024m_ten_gbe1_led_tx: in std_logic;
    expres4g1024m_ten_gbe1_led_up: in std_logic;
    expres4g1024m_ten_gbe1_rx_data: in std_logic_vector(63 downto 0);
    expres4g1024m_ten_gbe1_rx_end_of_frame: in std_logic;
    expres4g1024m_ten_gbe1_rx_size: in std_logic_vector(15 downto 0);
    expres4g1024m_ten_gbe1_rx_source_ip: in std_logic_vector(31 downto 0);
    expres4g1024m_ten_gbe1_rx_source_port: in std_logic_vector(15 downto 0);
    expres4g1024m_ten_gbe1_rx_valid: in std_logic;
    expres4g1024m_ten_gbe1_tx_ack: in std_logic;
    expres4g1024m_ten_gbe2_led_rx: in std_logic;
    expres4g1024m_ten_gbe2_led_tx: in std_logic;
    expres4g1024m_ten_gbe2_led_up: in std_logic;
    expres4g1024m_ten_gbe2_rx_data: in std_logic_vector(63 downto 0);
    expres4g1024m_ten_gbe2_rx_end_of_frame: in std_logic;
    expres4g1024m_ten_gbe2_rx_size: in std_logic_vector(15 downto 0);
    expres4g1024m_ten_gbe2_rx_source_ip: in std_logic_vector(31 downto 0);
    expres4g1024m_ten_gbe2_rx_source_port: in std_logic_vector(15 downto 0);
    expres4g1024m_ten_gbe2_rx_valid: in std_logic;
    expres4g1024m_ten_gbe2_tx_ack: in std_logic;
    expres4g1024m_vdif_framelen_w64_user_data_out: in std_logic_vector(31 downto 0);
    gateway_in: in std_logic_vector(7 downto 0);
    gateway_in1: in std_logic;
    gateway_in2: in std_logic;
    gateway_in3: in std_logic;
    gateway_in4: in std_logic_vector(15 downto 0);
    gateway_in5: in std_logic_vector(4 downto 0);
    gateway_in6: in std_logic_vector(4 downto 0);
    rst: in std_logic;
    expres4g1024m_adc_data_i_user_data_in: out std_logic_vector(31 downto 0);
    expres4g1024m_adc_data_q_user_data_in: out std_logic_vector(31 downto 0);
    expres4g1024m_led0_gateway: out std_logic;
    expres4g1024m_led1_gateway: out std_logic;
    expres4g1024m_led2_gateway: out std_logic;
    expres4g1024m_led3_gateway: out std_logic;
    expres4g1024m_led6_gateway: out std_logic;
    expres4g1024m_led7_gateway: out std_logic;
    expres4g1024m_rtc_time_user_data_in: out std_logic_vector(31 downto 0);
    expres4g1024m_status_user_data_in: out std_logic_vector(31 downto 0);
    expres4g1024m_ten_gbe1_rst: out std_logic;
    expres4g1024m_ten_gbe1_rx_ack: out std_logic;
    expres4g1024m_ten_gbe1_tx_data: out std_logic_vector(63 downto 0);
    expres4g1024m_ten_gbe1_tx_dest_ip: out std_logic_vector(31 downto 0);
    expres4g1024m_ten_gbe1_tx_dest_port: out std_logic_vector(15 downto 0);
    expres4g1024m_ten_gbe1_tx_discard: out std_logic;
    expres4g1024m_ten_gbe1_tx_end_of_frame: out std_logic;
    expres4g1024m_ten_gbe1_tx_valid: out std_logic;
    expres4g1024m_ten_gbe2_rst: out std_logic;
    expres4g1024m_ten_gbe2_rx_ack: out std_logic;
    expres4g1024m_ten_gbe2_tx_data: out std_logic_vector(63 downto 0);
    expres4g1024m_ten_gbe2_tx_dest_ip: out std_logic_vector(31 downto 0);
    expres4g1024m_ten_gbe2_tx_dest_port: out std_logic_vector(15 downto 0);
    expres4g1024m_ten_gbe2_tx_discard: out std_logic;
    expres4g1024m_ten_gbe2_tx_end_of_frame: out std_logic;
    expres4g1024m_ten_gbe2_tx_valid: out std_logic;
    expres4g1024m_twobit_data_i_user_data_in: out std_logic_vector(31 downto 0);
    expres4g1024m_twobit_data_q_user_data_in: out std_logic_vector(31 downto 0)
  );
end expres4g1024m_dw;

architecture structural of expres4g1024m_dw is
  signal clk_x0: std_logic;
  signal clk_x1: std_logic;
  signal dcm_clk0: std_logic;
  signal expres4g1024m_adc_user_data_valid_x0: std_logic;
  signal expres4g1024m_adc_user_datai0_x0: std_logic_vector(7 downto 0);
  signal expres4g1024m_adc_user_datai1_x0: std_logic_vector(7 downto 0);
  signal expres4g1024m_adc_user_datai2_x0: std_logic_vector(7 downto 0);
  signal expres4g1024m_adc_user_datai3_x0: std_logic_vector(7 downto 0);
  signal expres4g1024m_adc_user_dataq0_x0: std_logic_vector(7 downto 0);
  signal expres4g1024m_adc_user_dataq1_x0: std_logic_vector(7 downto 0);
  signal expres4g1024m_adc_user_dataq2_x0: std_logic_vector(7 downto 0);
  signal expres4g1024m_adc_user_dataq3_x0: std_logic_vector(7 downto 0);
  signal expres4g1024m_adc_user_outofrangei0_x0: std_logic;
  signal expres4g1024m_adc_user_outofrangei1_x0: std_logic;
  signal expres4g1024m_adc_user_outofrangeq0_x0: std_logic;
  signal expres4g1024m_adc_user_outofrangeq1_x0: std_logic;
  signal expres4g1024m_adc_user_sync0_x0: std_logic;
  signal expres4g1024m_adc_user_sync1_x0: std_logic;
  signal expres4g1024m_adc_user_sync2_x0: std_logic;
  signal expres4g1024m_adc_user_sync3_x0: std_logic;
  signal expres4g1024m_bit_levels_user_data_out_x0: std_logic_vector(31 downto 0);
  signal expres4g1024m_config_user_data_out_x0: std_logic_vector(31 downto 0);
  signal expres4g1024m_dest_ip_user_data_out_x0: std_logic_vector(31 downto 0);
  signal expres4g1024m_dest_port_offset_user_data_out_x0: std_logic_vector(31 downto 0);
  signal expres4g1024m_dest_port_user_data_out_x0: std_logic_vector(31 downto 0);
  signal expres4g1024m_national_semi_pll_user_data_out_x0: std_logic_vector(31 downto 0);
  signal expres4g1024m_rtc_settime_user_data_out_x0: std_logic_vector(31 downto 0);
  signal expres4g1024m_rtc_starttime_user_data_out_x0: std_logic_vector(31 downto 0);
  signal expres4g1024m_rtc_stoptime_user_data_out_x0: std_logic_vector(31 downto 0);
  signal expres4g1024m_ten_gbe1_led_rx_x0: std_logic;
  signal expres4g1024m_ten_gbe1_led_tx_x0: std_logic;
  signal expres4g1024m_ten_gbe1_led_up_x0: std_logic;
  signal expres4g1024m_ten_gbe1_rx_data_x0: std_logic_vector(63 downto 0);
  signal expres4g1024m_ten_gbe1_rx_end_of_frame_x0: std_logic;
  signal expres4g1024m_ten_gbe1_rx_size_x0: std_logic_vector(15 downto 0);
  signal expres4g1024m_ten_gbe1_rx_source_ip_x0: std_logic_vector(31 downto 0);
  signal expres4g1024m_ten_gbe1_rx_source_port_x0: std_logic_vector(15 downto 0);
  signal expres4g1024m_ten_gbe1_rx_valid_x0: std_logic;
  signal expres4g1024m_ten_gbe1_tx_ack_x0: std_logic;
  signal expres4g1024m_ten_gbe2_led_rx_x0: std_logic;
  signal expres4g1024m_ten_gbe2_led_tx_x0: std_logic;
  signal expres4g1024m_ten_gbe2_led_up_x0: std_logic;
  signal expres4g1024m_ten_gbe2_rx_data_x0: std_logic_vector(63 downto 0);
  signal expres4g1024m_ten_gbe2_rx_end_of_frame_x0: std_logic;
  signal expres4g1024m_ten_gbe2_rx_size_x0: std_logic_vector(15 downto 0);
  signal expres4g1024m_ten_gbe2_rx_source_ip_x0: std_logic_vector(31 downto 0);
  signal expres4g1024m_ten_gbe2_rx_source_port_x0: std_logic_vector(15 downto 0);
  signal expres4g1024m_ten_gbe2_rx_valid_x0: std_logic;
  signal expres4g1024m_ten_gbe2_tx_ack_x0: std_logic;
  signal expres4g1024m_vdif_framelen_w64_user_data_out_x0: std_logic_vector(31 downto 0);
  signal gateway_in1_x0: std_logic;
  signal gateway_in2_x0: std_logic;
  signal gateway_in3_x0: std_logic;
  signal gateway_in4_x0: std_logic_vector(15 downto 0);
  signal gateway_in5_x0: std_logic_vector(4 downto 0);
  signal gateway_in6_x0: std_logic_vector(4 downto 0);
  signal gateway_in_x0: std_logic_vector(7 downto 0);
  signal rst_x0: std_logic;
  signal sysgen_dut_expres4g1024m_adc_data_i_user_data_in: std_logic_vector(31 downto 0);
  signal sysgen_dut_expres4g1024m_adc_data_q_user_data_in: std_logic_vector(31 downto 0);
  signal sysgen_dut_expres4g1024m_led0_gateway: std_logic;
  signal sysgen_dut_expres4g1024m_led1_gateway: std_logic;
  signal sysgen_dut_expres4g1024m_led2_gateway: std_logic;
  signal sysgen_dut_expres4g1024m_led3_gateway: std_logic;
  signal sysgen_dut_expres4g1024m_led6_gateway: std_logic;
  signal sysgen_dut_expres4g1024m_led7_gateway: std_logic;
  signal sysgen_dut_expres4g1024m_rtc_time_user_data_in: std_logic_vector(31 downto 0);
  signal sysgen_dut_expres4g1024m_status_user_data_in: std_logic_vector(31 downto 0);
  signal sysgen_dut_expres4g1024m_ten_gbe1_rst: std_logic;
  signal sysgen_dut_expres4g1024m_ten_gbe1_rx_ack: std_logic;
  signal sysgen_dut_expres4g1024m_ten_gbe1_tx_data: std_logic_vector(63 downto 0);
  signal sysgen_dut_expres4g1024m_ten_gbe1_tx_dest_ip: std_logic_vector(31 downto 0);
  signal sysgen_dut_expres4g1024m_ten_gbe1_tx_dest_port: std_logic_vector(15 downto 0);
  signal sysgen_dut_expres4g1024m_ten_gbe1_tx_discard: std_logic;
  signal sysgen_dut_expres4g1024m_ten_gbe1_tx_end_of_frame: std_logic;
  signal sysgen_dut_expres4g1024m_ten_gbe1_tx_valid: std_logic;
  signal sysgen_dut_expres4g1024m_ten_gbe2_rst: std_logic;
  signal sysgen_dut_expres4g1024m_ten_gbe2_rx_ack: std_logic;
  signal sysgen_dut_expres4g1024m_ten_gbe2_tx_data: std_logic_vector(63 downto 0);
  signal sysgen_dut_expres4g1024m_ten_gbe2_tx_dest_ip: std_logic_vector(31 downto 0);
  signal sysgen_dut_expres4g1024m_ten_gbe2_tx_dest_port: std_logic_vector(15 downto 0);
  signal sysgen_dut_expres4g1024m_ten_gbe2_tx_discard: std_logic;
  signal sysgen_dut_expres4g1024m_ten_gbe2_tx_end_of_frame: std_logic;
  signal sysgen_dut_expres4g1024m_ten_gbe2_tx_valid: std_logic;
  signal sysgen_dut_expres4g1024m_twobit_data_i_user_data_in: std_logic_vector(31 downto 0);
  signal sysgen_dut_expres4g1024m_twobit_data_q_user_data_in: std_logic_vector(31 downto 0);

begin
  clk_x1 <= clk;
  expres4g1024m_adc_user_data_valid_x0 <= expres4g1024m_adc_user_data_valid;
  expres4g1024m_adc_user_datai0_x0 <= expres4g1024m_adc_user_datai0;
  expres4g1024m_adc_user_datai1_x0 <= expres4g1024m_adc_user_datai1;
  expres4g1024m_adc_user_datai2_x0 <= expres4g1024m_adc_user_datai2;
  expres4g1024m_adc_user_datai3_x0 <= expres4g1024m_adc_user_datai3;
  expres4g1024m_adc_user_dataq0_x0 <= expres4g1024m_adc_user_dataq0;
  expres4g1024m_adc_user_dataq1_x0 <= expres4g1024m_adc_user_dataq1;
  expres4g1024m_adc_user_dataq2_x0 <= expres4g1024m_adc_user_dataq2;
  expres4g1024m_adc_user_dataq3_x0 <= expres4g1024m_adc_user_dataq3;
  expres4g1024m_adc_user_outofrangei0_x0 <= expres4g1024m_adc_user_outofrangei0;
  expres4g1024m_adc_user_outofrangei1_x0 <= expres4g1024m_adc_user_outofrangei1;
  expres4g1024m_adc_user_outofrangeq0_x0 <= expres4g1024m_adc_user_outofrangeq0;
  expres4g1024m_adc_user_outofrangeq1_x0 <= expres4g1024m_adc_user_outofrangeq1;
  expres4g1024m_adc_user_sync0_x0 <= expres4g1024m_adc_user_sync0;
  expres4g1024m_adc_user_sync1_x0 <= expres4g1024m_adc_user_sync1;
  expres4g1024m_adc_user_sync2_x0 <= expres4g1024m_adc_user_sync2;
  expres4g1024m_adc_user_sync3_x0 <= expres4g1024m_adc_user_sync3;
  expres4g1024m_bit_levels_user_data_out_x0 <= expres4g1024m_bit_levels_user_data_out;
  expres4g1024m_config_user_data_out_x0 <= expres4g1024m_config_user_data_out;
  expres4g1024m_dest_ip_user_data_out_x0 <= expres4g1024m_dest_ip_user_data_out;
  expres4g1024m_dest_port_offset_user_data_out_x0 <= expres4g1024m_dest_port_offset_user_data_out;
  expres4g1024m_dest_port_user_data_out_x0 <= expres4g1024m_dest_port_user_data_out;
  expres4g1024m_national_semi_pll_user_data_out_x0 <= expres4g1024m_national_semi_pll_user_data_out;
  expres4g1024m_rtc_settime_user_data_out_x0 <= expres4g1024m_rtc_settime_user_data_out;
  expres4g1024m_rtc_starttime_user_data_out_x0 <= expres4g1024m_rtc_starttime_user_data_out;
  expres4g1024m_rtc_stoptime_user_data_out_x0 <= expres4g1024m_rtc_stoptime_user_data_out;
  expres4g1024m_ten_gbe1_led_rx_x0 <= expres4g1024m_ten_gbe1_led_rx;
  expres4g1024m_ten_gbe1_led_tx_x0 <= expres4g1024m_ten_gbe1_led_tx;
  expres4g1024m_ten_gbe1_led_up_x0 <= expres4g1024m_ten_gbe1_led_up;
  expres4g1024m_ten_gbe1_rx_data_x0 <= expres4g1024m_ten_gbe1_rx_data;
  expres4g1024m_ten_gbe1_rx_end_of_frame_x0 <= expres4g1024m_ten_gbe1_rx_end_of_frame;
  expres4g1024m_ten_gbe1_rx_size_x0 <= expres4g1024m_ten_gbe1_rx_size;
  expres4g1024m_ten_gbe1_rx_source_ip_x0 <= expres4g1024m_ten_gbe1_rx_source_ip;
  expres4g1024m_ten_gbe1_rx_source_port_x0 <= expres4g1024m_ten_gbe1_rx_source_port;
  expres4g1024m_ten_gbe1_rx_valid_x0 <= expres4g1024m_ten_gbe1_rx_valid;
  expres4g1024m_ten_gbe1_tx_ack_x0 <= expres4g1024m_ten_gbe1_tx_ack;
  expres4g1024m_ten_gbe2_led_rx_x0 <= expres4g1024m_ten_gbe2_led_rx;
  expres4g1024m_ten_gbe2_led_tx_x0 <= expres4g1024m_ten_gbe2_led_tx;
  expres4g1024m_ten_gbe2_led_up_x0 <= expres4g1024m_ten_gbe2_led_up;
  expres4g1024m_ten_gbe2_rx_data_x0 <= expres4g1024m_ten_gbe2_rx_data;
  expres4g1024m_ten_gbe2_rx_end_of_frame_x0 <= expres4g1024m_ten_gbe2_rx_end_of_frame;
  expres4g1024m_ten_gbe2_rx_size_x0 <= expres4g1024m_ten_gbe2_rx_size;
  expres4g1024m_ten_gbe2_rx_source_ip_x0 <= expres4g1024m_ten_gbe2_rx_source_ip;
  expres4g1024m_ten_gbe2_rx_source_port_x0 <= expres4g1024m_ten_gbe2_rx_source_port;
  expres4g1024m_ten_gbe2_rx_valid_x0 <= expres4g1024m_ten_gbe2_rx_valid;
  expres4g1024m_ten_gbe2_tx_ack_x0 <= expres4g1024m_ten_gbe2_tx_ack;
  expres4g1024m_vdif_framelen_w64_user_data_out_x0 <= expres4g1024m_vdif_framelen_w64_user_data_out;
  gateway_in_x0 <= gateway_in;
  gateway_in1_x0 <= gateway_in1;
  gateway_in2_x0 <= gateway_in2;
  gateway_in3_x0 <= gateway_in3;
  gateway_in4_x0 <= gateway_in4;
  gateway_in5_x0 <= gateway_in5;
  gateway_in6_x0 <= gateway_in6;
  rst_x0 <= rst;
  expres4g1024m_adc_data_i_user_data_in <= sysgen_dut_expres4g1024m_adc_data_i_user_data_in;
  expres4g1024m_adc_data_q_user_data_in <= sysgen_dut_expres4g1024m_adc_data_q_user_data_in;
  expres4g1024m_led0_gateway <= sysgen_dut_expres4g1024m_led0_gateway;
  expres4g1024m_led1_gateway <= sysgen_dut_expres4g1024m_led1_gateway;
  expres4g1024m_led2_gateway <= sysgen_dut_expres4g1024m_led2_gateway;
  expres4g1024m_led3_gateway <= sysgen_dut_expres4g1024m_led3_gateway;
  expres4g1024m_led6_gateway <= sysgen_dut_expres4g1024m_led6_gateway;
  expres4g1024m_led7_gateway <= sysgen_dut_expres4g1024m_led7_gateway;
  expres4g1024m_rtc_time_user_data_in <= sysgen_dut_expres4g1024m_rtc_time_user_data_in;
  expres4g1024m_status_user_data_in <= sysgen_dut_expres4g1024m_status_user_data_in;
  expres4g1024m_ten_gbe1_rst <= sysgen_dut_expres4g1024m_ten_gbe1_rst;
  expres4g1024m_ten_gbe1_rx_ack <= sysgen_dut_expres4g1024m_ten_gbe1_rx_ack;
  expres4g1024m_ten_gbe1_tx_data <= sysgen_dut_expres4g1024m_ten_gbe1_tx_data;
  expres4g1024m_ten_gbe1_tx_dest_ip <= sysgen_dut_expres4g1024m_ten_gbe1_tx_dest_ip;
  expres4g1024m_ten_gbe1_tx_dest_port <= sysgen_dut_expres4g1024m_ten_gbe1_tx_dest_port;
  expres4g1024m_ten_gbe1_tx_discard <= sysgen_dut_expres4g1024m_ten_gbe1_tx_discard;
  expres4g1024m_ten_gbe1_tx_end_of_frame <= sysgen_dut_expres4g1024m_ten_gbe1_tx_end_of_frame;
  expres4g1024m_ten_gbe1_tx_valid <= sysgen_dut_expres4g1024m_ten_gbe1_tx_valid;
  expres4g1024m_ten_gbe2_rst <= sysgen_dut_expres4g1024m_ten_gbe2_rst;
  expres4g1024m_ten_gbe2_rx_ack <= sysgen_dut_expres4g1024m_ten_gbe2_rx_ack;
  expres4g1024m_ten_gbe2_tx_data <= sysgen_dut_expres4g1024m_ten_gbe2_tx_data;
  expres4g1024m_ten_gbe2_tx_dest_ip <= sysgen_dut_expres4g1024m_ten_gbe2_tx_dest_ip;
  expres4g1024m_ten_gbe2_tx_dest_port <= sysgen_dut_expres4g1024m_ten_gbe2_tx_dest_port;
  expres4g1024m_ten_gbe2_tx_discard <= sysgen_dut_expres4g1024m_ten_gbe2_tx_discard;
  expres4g1024m_ten_gbe2_tx_end_of_frame <= sysgen_dut_expres4g1024m_ten_gbe2_tx_end_of_frame;
  expres4g1024m_ten_gbe2_tx_valid <= sysgen_dut_expres4g1024m_ten_gbe2_tx_valid;
  expres4g1024m_twobit_data_i_user_data_in <= sysgen_dut_expres4g1024m_twobit_data_i_user_data_in;
  expres4g1024m_twobit_data_q_user_data_in <= sysgen_dut_expres4g1024m_twobit_data_q_user_data_in;

  dcm: entity work.xlclockgenerator
    generic map (
      ensure_clks_stable => false
    )
    port map (
      clk => clk_x1,
      rst => rst_x0,
      clk0 => dcm_clk0
    );

  sysgen_dut: entity work.expres4g1024m_cw
    port map (
      clk => dcm_clk0,
      expres4g1024m_adc_user_data_valid => expres4g1024m_adc_user_data_valid_x0,
      expres4g1024m_adc_user_datai0 => expres4g1024m_adc_user_datai0_x0,
      expres4g1024m_adc_user_datai1 => expres4g1024m_adc_user_datai1_x0,
      expres4g1024m_adc_user_datai2 => expres4g1024m_adc_user_datai2_x0,
      expres4g1024m_adc_user_datai3 => expres4g1024m_adc_user_datai3_x0,
      expres4g1024m_adc_user_dataq0 => expres4g1024m_adc_user_dataq0_x0,
      expres4g1024m_adc_user_dataq1 => expres4g1024m_adc_user_dataq1_x0,
      expres4g1024m_adc_user_dataq2 => expres4g1024m_adc_user_dataq2_x0,
      expres4g1024m_adc_user_dataq3 => expres4g1024m_adc_user_dataq3_x0,
      expres4g1024m_adc_user_outofrangei0 => expres4g1024m_adc_user_outofrangei0_x0,
      expres4g1024m_adc_user_outofrangei1 => expres4g1024m_adc_user_outofrangei1_x0,
      expres4g1024m_adc_user_outofrangeq0 => expres4g1024m_adc_user_outofrangeq0_x0,
      expres4g1024m_adc_user_outofrangeq1 => expres4g1024m_adc_user_outofrangeq1_x0,
      expres4g1024m_adc_user_sync0 => expres4g1024m_adc_user_sync0_x0,
      expres4g1024m_adc_user_sync1 => expres4g1024m_adc_user_sync1_x0,
      expres4g1024m_adc_user_sync2 => expres4g1024m_adc_user_sync2_x0,
      expres4g1024m_adc_user_sync3 => expres4g1024m_adc_user_sync3_x0,
      expres4g1024m_bit_levels_user_data_out => expres4g1024m_bit_levels_user_data_out_x0,
      expres4g1024m_config_user_data_out => expres4g1024m_config_user_data_out_x0,
      expres4g1024m_dest_ip_user_data_out => expres4g1024m_dest_ip_user_data_out_x0,
      expres4g1024m_dest_port_offset_user_data_out => expres4g1024m_dest_port_offset_user_data_out_x0,
      expres4g1024m_dest_port_user_data_out => expres4g1024m_dest_port_user_data_out_x0,
      expres4g1024m_national_semi_pll_user_data_out => expres4g1024m_national_semi_pll_user_data_out_x0,
      expres4g1024m_rtc_settime_user_data_out => expres4g1024m_rtc_settime_user_data_out_x0,
      expres4g1024m_rtc_starttime_user_data_out => expres4g1024m_rtc_starttime_user_data_out_x0,
      expres4g1024m_rtc_stoptime_user_data_out => expres4g1024m_rtc_stoptime_user_data_out_x0,
      expres4g1024m_ten_gbe1_led_rx => expres4g1024m_ten_gbe1_led_rx_x0,
      expres4g1024m_ten_gbe1_led_tx => expres4g1024m_ten_gbe1_led_tx_x0,
      expres4g1024m_ten_gbe1_led_up => expres4g1024m_ten_gbe1_led_up_x0,
      expres4g1024m_ten_gbe1_rx_data => expres4g1024m_ten_gbe1_rx_data_x0,
      expres4g1024m_ten_gbe1_rx_end_of_frame => expres4g1024m_ten_gbe1_rx_end_of_frame_x0,
      expres4g1024m_ten_gbe1_rx_size => expres4g1024m_ten_gbe1_rx_size_x0,
      expres4g1024m_ten_gbe1_rx_source_ip => expres4g1024m_ten_gbe1_rx_source_ip_x0,
      expres4g1024m_ten_gbe1_rx_source_port => expres4g1024m_ten_gbe1_rx_source_port_x0,
      expres4g1024m_ten_gbe1_rx_valid => expres4g1024m_ten_gbe1_rx_valid_x0,
      expres4g1024m_ten_gbe1_tx_ack => expres4g1024m_ten_gbe1_tx_ack_x0,
      expres4g1024m_ten_gbe2_led_rx => expres4g1024m_ten_gbe2_led_rx_x0,
      expres4g1024m_ten_gbe2_led_tx => expres4g1024m_ten_gbe2_led_tx_x0,
      expres4g1024m_ten_gbe2_led_up => expres4g1024m_ten_gbe2_led_up_x0,
      expres4g1024m_ten_gbe2_rx_data => expres4g1024m_ten_gbe2_rx_data_x0,
      expres4g1024m_ten_gbe2_rx_end_of_frame => expres4g1024m_ten_gbe2_rx_end_of_frame_x0,
      expres4g1024m_ten_gbe2_rx_size => expres4g1024m_ten_gbe2_rx_size_x0,
      expres4g1024m_ten_gbe2_rx_source_ip => expres4g1024m_ten_gbe2_rx_source_ip_x0,
      expres4g1024m_ten_gbe2_rx_source_port => expres4g1024m_ten_gbe2_rx_source_port_x0,
      expres4g1024m_ten_gbe2_rx_valid => expres4g1024m_ten_gbe2_rx_valid_x0,
      expres4g1024m_ten_gbe2_tx_ack => expres4g1024m_ten_gbe2_tx_ack_x0,
      expres4g1024m_vdif_framelen_w64_user_data_out => expres4g1024m_vdif_framelen_w64_user_data_out_x0,
      gateway_in => gateway_in_x0,
      gateway_in1 => gateway_in1_x0,
      gateway_in2 => gateway_in2_x0,
      gateway_in3 => gateway_in3_x0,
      gateway_in4 => gateway_in4_x0,
      gateway_in5 => gateway_in5_x0,
      gateway_in6 => gateway_in6_x0,
      expres4g1024m_adc_data_i_user_data_in => sysgen_dut_expres4g1024m_adc_data_i_user_data_in,
      expres4g1024m_adc_data_q_user_data_in => sysgen_dut_expres4g1024m_adc_data_q_user_data_in,
      expres4g1024m_led0_gateway => sysgen_dut_expres4g1024m_led0_gateway,
      expres4g1024m_led1_gateway => sysgen_dut_expres4g1024m_led1_gateway,
      expres4g1024m_led2_gateway => sysgen_dut_expres4g1024m_led2_gateway,
      expres4g1024m_led3_gateway => sysgen_dut_expres4g1024m_led3_gateway,
      expres4g1024m_led6_gateway => sysgen_dut_expres4g1024m_led6_gateway,
      expres4g1024m_led7_gateway => sysgen_dut_expres4g1024m_led7_gateway,
      expres4g1024m_rtc_time_user_data_in => sysgen_dut_expres4g1024m_rtc_time_user_data_in,
      expres4g1024m_status_user_data_in => sysgen_dut_expres4g1024m_status_user_data_in,
      expres4g1024m_ten_gbe1_rst => sysgen_dut_expres4g1024m_ten_gbe1_rst,
      expres4g1024m_ten_gbe1_rx_ack => sysgen_dut_expres4g1024m_ten_gbe1_rx_ack,
      expres4g1024m_ten_gbe1_tx_data => sysgen_dut_expres4g1024m_ten_gbe1_tx_data,
      expres4g1024m_ten_gbe1_tx_dest_ip => sysgen_dut_expres4g1024m_ten_gbe1_tx_dest_ip,
      expres4g1024m_ten_gbe1_tx_dest_port => sysgen_dut_expres4g1024m_ten_gbe1_tx_dest_port,
      expres4g1024m_ten_gbe1_tx_discard => sysgen_dut_expres4g1024m_ten_gbe1_tx_discard,
      expres4g1024m_ten_gbe1_tx_end_of_frame => sysgen_dut_expres4g1024m_ten_gbe1_tx_end_of_frame,
      expres4g1024m_ten_gbe1_tx_valid => sysgen_dut_expres4g1024m_ten_gbe1_tx_valid,
      expres4g1024m_ten_gbe2_rst => sysgen_dut_expres4g1024m_ten_gbe2_rst,
      expres4g1024m_ten_gbe2_rx_ack => sysgen_dut_expres4g1024m_ten_gbe2_rx_ack,
      expres4g1024m_ten_gbe2_tx_data => sysgen_dut_expres4g1024m_ten_gbe2_tx_data,
      expres4g1024m_ten_gbe2_tx_dest_ip => sysgen_dut_expres4g1024m_ten_gbe2_tx_dest_ip,
      expres4g1024m_ten_gbe2_tx_dest_port => sysgen_dut_expres4g1024m_ten_gbe2_tx_dest_port,
      expres4g1024m_ten_gbe2_tx_discard => sysgen_dut_expres4g1024m_ten_gbe2_tx_discard,
      expres4g1024m_ten_gbe2_tx_end_of_frame => sysgen_dut_expres4g1024m_ten_gbe2_tx_end_of_frame,
      expres4g1024m_ten_gbe2_tx_valid => sysgen_dut_expres4g1024m_ten_gbe2_tx_valid,
      expres4g1024m_twobit_data_i_user_data_in => sysgen_dut_expres4g1024m_twobit_data_i_user_data_in,
      expres4g1024m_twobit_data_q_user_data_in => sysgen_dut_expres4g1024m_twobit_data_q_user_data_in
    );

end structural;
