
-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
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-- Inc., is distributed under license from Xilinx, Inc., and may be used,
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-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
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-- Any modifications that are made to the source code are done at the user's
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-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
-- The following code must appear in the VHDL architecture header:

------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
component expres4g1024m_cw  port (
    ce: in std_logic := '1';
    clk: in std_logic;
    expres4g1024m_adc_user_data_valid: in std_logic;
    expres4g1024m_adc_user_datai0: in std_logic_vector(7 downto 0);
    expres4g1024m_adc_user_datai1: in std_logic_vector(7 downto 0);
    expres4g1024m_adc_user_datai2: in std_logic_vector(7 downto 0);
    expres4g1024m_adc_user_datai3: in std_logic_vector(7 downto 0);
    expres4g1024m_adc_user_dataq0: in std_logic_vector(7 downto 0);
    expres4g1024m_adc_user_dataq1: in std_logic_vector(7 downto 0);
    expres4g1024m_adc_user_dataq2: in std_logic_vector(7 downto 0);
    expres4g1024m_adc_user_dataq3: in std_logic_vector(7 downto 0);
    expres4g1024m_adc_user_outofrangei0: in std_logic;
    expres4g1024m_adc_user_outofrangei1: in std_logic;
    expres4g1024m_adc_user_outofrangeq0: in std_logic;
    expres4g1024m_adc_user_outofrangeq1: in std_logic;
    expres4g1024m_adc_user_sync0: in std_logic;
    expres4g1024m_adc_user_sync1: in std_logic;
    expres4g1024m_adc_user_sync2: in std_logic;
    expres4g1024m_adc_user_sync3: in std_logic;
    expres4g1024m_bit_levels_user_data_out: in std_logic_vector(31 downto 0);
    expres4g1024m_config_user_data_out: in std_logic_vector(31 downto 0);
    expres4g1024m_dest_ip_user_data_out: in std_logic_vector(31 downto 0);
    expres4g1024m_dest_port_offset_user_data_out: in std_logic_vector(31 downto 0);
    expres4g1024m_dest_port_user_data_out: in std_logic_vector(31 downto 0);
    expres4g1024m_national_semi_pll_user_data_out: in std_logic_vector(31 downto 0);
    expres4g1024m_rtc_settime_user_data_out: in std_logic_vector(31 downto 0);
    expres4g1024m_rtc_starttime_user_data_out: in std_logic_vector(31 downto 0);
    expres4g1024m_rtc_stoptime_user_data_out: in std_logic_vector(31 downto 0);
    expres4g1024m_ten_gbe1_led_rx: in std_logic;
    expres4g1024m_ten_gbe1_led_tx: in std_logic;
    expres4g1024m_ten_gbe1_led_up: in std_logic;
    expres4g1024m_ten_gbe1_rx_data: in std_logic_vector(63 downto 0);
    expres4g1024m_ten_gbe1_rx_end_of_frame: in std_logic;
    expres4g1024m_ten_gbe1_rx_size: in std_logic_vector(15 downto 0);
    expres4g1024m_ten_gbe1_rx_source_ip: in std_logic_vector(31 downto 0);
    expres4g1024m_ten_gbe1_rx_source_port: in std_logic_vector(15 downto 0);
    expres4g1024m_ten_gbe1_rx_valid: in std_logic;
    expres4g1024m_ten_gbe1_tx_ack: in std_logic;
    expres4g1024m_ten_gbe2_led_rx: in std_logic;
    expres4g1024m_ten_gbe2_led_tx: in std_logic;
    expres4g1024m_ten_gbe2_led_up: in std_logic;
    expres4g1024m_ten_gbe2_rx_data: in std_logic_vector(63 downto 0);
    expres4g1024m_ten_gbe2_rx_end_of_frame: in std_logic;
    expres4g1024m_ten_gbe2_rx_size: in std_logic_vector(15 downto 0);
    expres4g1024m_ten_gbe2_rx_source_ip: in std_logic_vector(31 downto 0);
    expres4g1024m_ten_gbe2_rx_source_port: in std_logic_vector(15 downto 0);
    expres4g1024m_ten_gbe2_rx_valid: in std_logic;
    expres4g1024m_ten_gbe2_tx_ack: in std_logic;
    expres4g1024m_vdif_framelen_w64_user_data_out: in std_logic_vector(31 downto 0);
    gateway_in: in std_logic_vector(7 downto 0);
    gateway_in1: in std_logic;
    gateway_in2: in std_logic;
    gateway_in3: in std_logic;
    gateway_in4: in std_logic_vector(15 downto 0);
    gateway_in5: in std_logic_vector(4 downto 0);
    gateway_in6: in std_logic_vector(4 downto 0);
    expres4g1024m_adc_data_i_user_data_in: out std_logic_vector(31 downto 0);
    expres4g1024m_adc_data_q_user_data_in: out std_logic_vector(31 downto 0);
    expres4g1024m_led0_gateway: out std_logic;
    expres4g1024m_led1_gateway: out std_logic;
    expres4g1024m_led2_gateway: out std_logic;
    expres4g1024m_led3_gateway: out std_logic;
    expres4g1024m_led6_gateway: out std_logic;
    expres4g1024m_led7_gateway: out std_logic;
    expres4g1024m_rtc_time_user_data_in: out std_logic_vector(31 downto 0);
    expres4g1024m_status_user_data_in: out std_logic_vector(31 downto 0);
    expres4g1024m_ten_gbe1_rst: out std_logic;
    expres4g1024m_ten_gbe1_rx_ack: out std_logic;
    expres4g1024m_ten_gbe1_tx_data: out std_logic_vector(63 downto 0);
    expres4g1024m_ten_gbe1_tx_dest_ip: out std_logic_vector(31 downto 0);
    expres4g1024m_ten_gbe1_tx_dest_port: out std_logic_vector(15 downto 0);
    expres4g1024m_ten_gbe1_tx_discard: out std_logic;
    expres4g1024m_ten_gbe1_tx_end_of_frame: out std_logic;
    expres4g1024m_ten_gbe1_tx_valid: out std_logic;
    expres4g1024m_ten_gbe2_rst: out std_logic;
    expres4g1024m_ten_gbe2_rx_ack: out std_logic;
    expres4g1024m_ten_gbe2_tx_data: out std_logic_vector(63 downto 0);
    expres4g1024m_ten_gbe2_tx_dest_ip: out std_logic_vector(31 downto 0);
    expres4g1024m_ten_gbe2_tx_dest_port: out std_logic_vector(15 downto 0);
    expres4g1024m_ten_gbe2_tx_discard: out std_logic;
    expres4g1024m_ten_gbe2_tx_end_of_frame: out std_logic;
    expres4g1024m_ten_gbe2_tx_valid: out std_logic;
    expres4g1024m_twobit_data_i_user_data_in: out std_logic_vector(31 downto 0);
    expres4g1024m_twobit_data_q_user_data_in: out std_logic_vector(31 downto 0)
  );
end component;
-- COMP_TAG_END ------ End COMPONENT Declaration ------------

-- The following code must appear in the VHDL architecture
-- body.  Substitute your own instance name and net names.

------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
your_instance_name : expres4g1024m_cw
  port map (
    ce => ce,
    clk => clk,
    expres4g1024m_adc_user_data_valid => expres4g1024m_adc_user_data_valid,
    expres4g1024m_adc_user_datai0 => expres4g1024m_adc_user_datai0,
    expres4g1024m_adc_user_datai1 => expres4g1024m_adc_user_datai1,
    expres4g1024m_adc_user_datai2 => expres4g1024m_adc_user_datai2,
    expres4g1024m_adc_user_datai3 => expres4g1024m_adc_user_datai3,
    expres4g1024m_adc_user_dataq0 => expres4g1024m_adc_user_dataq0,
    expres4g1024m_adc_user_dataq1 => expres4g1024m_adc_user_dataq1,
    expres4g1024m_adc_user_dataq2 => expres4g1024m_adc_user_dataq2,
    expres4g1024m_adc_user_dataq3 => expres4g1024m_adc_user_dataq3,
    expres4g1024m_adc_user_outofrangei0 => expres4g1024m_adc_user_outofrangei0,
    expres4g1024m_adc_user_outofrangei1 => expres4g1024m_adc_user_outofrangei1,
    expres4g1024m_adc_user_outofrangeq0 => expres4g1024m_adc_user_outofrangeq0,
    expres4g1024m_adc_user_outofrangeq1 => expres4g1024m_adc_user_outofrangeq1,
    expres4g1024m_adc_user_sync0 => expres4g1024m_adc_user_sync0,
    expres4g1024m_adc_user_sync1 => expres4g1024m_adc_user_sync1,
    expres4g1024m_adc_user_sync2 => expres4g1024m_adc_user_sync2,
    expres4g1024m_adc_user_sync3 => expres4g1024m_adc_user_sync3,
    expres4g1024m_bit_levels_user_data_out => expres4g1024m_bit_levels_user_data_out,
    expres4g1024m_config_user_data_out => expres4g1024m_config_user_data_out,
    expres4g1024m_dest_ip_user_data_out => expres4g1024m_dest_ip_user_data_out,
    expres4g1024m_dest_port_offset_user_data_out => expres4g1024m_dest_port_offset_user_data_out,
    expres4g1024m_dest_port_user_data_out => expres4g1024m_dest_port_user_data_out,
    expres4g1024m_national_semi_pll_user_data_out => expres4g1024m_national_semi_pll_user_data_out,
    expres4g1024m_rtc_settime_user_data_out => expres4g1024m_rtc_settime_user_data_out,
    expres4g1024m_rtc_starttime_user_data_out => expres4g1024m_rtc_starttime_user_data_out,
    expres4g1024m_rtc_stoptime_user_data_out => expres4g1024m_rtc_stoptime_user_data_out,
    expres4g1024m_ten_gbe1_led_rx => expres4g1024m_ten_gbe1_led_rx,
    expres4g1024m_ten_gbe1_led_tx => expres4g1024m_ten_gbe1_led_tx,
    expres4g1024m_ten_gbe1_led_up => expres4g1024m_ten_gbe1_led_up,
    expres4g1024m_ten_gbe1_rx_data => expres4g1024m_ten_gbe1_rx_data,
    expres4g1024m_ten_gbe1_rx_end_of_frame => expres4g1024m_ten_gbe1_rx_end_of_frame,
    expres4g1024m_ten_gbe1_rx_size => expres4g1024m_ten_gbe1_rx_size,
    expres4g1024m_ten_gbe1_rx_source_ip => expres4g1024m_ten_gbe1_rx_source_ip,
    expres4g1024m_ten_gbe1_rx_source_port => expres4g1024m_ten_gbe1_rx_source_port,
    expres4g1024m_ten_gbe1_rx_valid => expres4g1024m_ten_gbe1_rx_valid,
    expres4g1024m_ten_gbe1_tx_ack => expres4g1024m_ten_gbe1_tx_ack,
    expres4g1024m_ten_gbe2_led_rx => expres4g1024m_ten_gbe2_led_rx,
    expres4g1024m_ten_gbe2_led_tx => expres4g1024m_ten_gbe2_led_tx,
    expres4g1024m_ten_gbe2_led_up => expres4g1024m_ten_gbe2_led_up,
    expres4g1024m_ten_gbe2_rx_data => expres4g1024m_ten_gbe2_rx_data,
    expres4g1024m_ten_gbe2_rx_end_of_frame => expres4g1024m_ten_gbe2_rx_end_of_frame,
    expres4g1024m_ten_gbe2_rx_size => expres4g1024m_ten_gbe2_rx_size,
    expres4g1024m_ten_gbe2_rx_source_ip => expres4g1024m_ten_gbe2_rx_source_ip,
    expres4g1024m_ten_gbe2_rx_source_port => expres4g1024m_ten_gbe2_rx_source_port,
    expres4g1024m_ten_gbe2_rx_valid => expres4g1024m_ten_gbe2_rx_valid,
    expres4g1024m_ten_gbe2_tx_ack => expres4g1024m_ten_gbe2_tx_ack,
    expres4g1024m_vdif_framelen_w64_user_data_out => expres4g1024m_vdif_framelen_w64_user_data_out,
    gateway_in => gateway_in,
    gateway_in1 => gateway_in1,
    gateway_in2 => gateway_in2,
    gateway_in3 => gateway_in3,
    gateway_in4 => gateway_in4,
    gateway_in5 => gateway_in5,
    gateway_in6 => gateway_in6,
    expres4g1024m_adc_data_i_user_data_in => expres4g1024m_adc_data_i_user_data_in,
    expres4g1024m_adc_data_q_user_data_in => expres4g1024m_adc_data_q_user_data_in,
    expres4g1024m_led0_gateway => expres4g1024m_led0_gateway,
    expres4g1024m_led1_gateway => expres4g1024m_led1_gateway,
    expres4g1024m_led2_gateway => expres4g1024m_led2_gateway,
    expres4g1024m_led3_gateway => expres4g1024m_led3_gateway,
    expres4g1024m_led6_gateway => expres4g1024m_led6_gateway,
    expres4g1024m_led7_gateway => expres4g1024m_led7_gateway,
    expres4g1024m_rtc_time_user_data_in => expres4g1024m_rtc_time_user_data_in,
    expres4g1024m_status_user_data_in => expres4g1024m_status_user_data_in,
    expres4g1024m_ten_gbe1_rst => expres4g1024m_ten_gbe1_rst,
    expres4g1024m_ten_gbe1_rx_ack => expres4g1024m_ten_gbe1_rx_ack,
    expres4g1024m_ten_gbe1_tx_data => expres4g1024m_ten_gbe1_tx_data,
    expres4g1024m_ten_gbe1_tx_dest_ip => expres4g1024m_ten_gbe1_tx_dest_ip,
    expres4g1024m_ten_gbe1_tx_dest_port => expres4g1024m_ten_gbe1_tx_dest_port,
    expres4g1024m_ten_gbe1_tx_discard => expres4g1024m_ten_gbe1_tx_discard,
    expres4g1024m_ten_gbe1_tx_end_of_frame => expres4g1024m_ten_gbe1_tx_end_of_frame,
    expres4g1024m_ten_gbe1_tx_valid => expres4g1024m_ten_gbe1_tx_valid,
    expres4g1024m_ten_gbe2_rst => expres4g1024m_ten_gbe2_rst,
    expres4g1024m_ten_gbe2_rx_ack => expres4g1024m_ten_gbe2_rx_ack,
    expres4g1024m_ten_gbe2_tx_data => expres4g1024m_ten_gbe2_tx_data,
    expres4g1024m_ten_gbe2_tx_dest_ip => expres4g1024m_ten_gbe2_tx_dest_ip,
    expres4g1024m_ten_gbe2_tx_dest_port => expres4g1024m_ten_gbe2_tx_dest_port,
    expres4g1024m_ten_gbe2_tx_discard => expres4g1024m_ten_gbe2_tx_discard,
    expres4g1024m_ten_gbe2_tx_end_of_frame => expres4g1024m_ten_gbe2_tx_end_of_frame,
    expres4g1024m_ten_gbe2_tx_valid => expres4g1024m_ten_gbe2_tx_valid,
    expres4g1024m_twobit_data_i_user_data_in => expres4g1024m_twobit_data_i_user_data_in,
    expres4g1024m_twobit_data_q_user_data_in => expres4g1024m_twobit_data_q_user_data_in);
-- INST_TAG_END ------ End INSTANTIATION Template ------------
