--------------------------------------------------------------------------------
--     This file is owned and controlled by Xilinx and must be used           --
--     solely for design, simulation, implementation and creation of          --
--     design files limited to Xilinx devices or technologies. Use            --
--     with non-Xilinx devices or technologies is expressly prohibited        --
--     and immediately terminates your license.                               --
--                                                                            --
--     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"          --
--     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                --
--     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION        --
--     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION            --
--     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS              --
--     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                --
--     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE       --
--     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY               --
--     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                --
--     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR         --
--     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF        --
--     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS        --
--     FOR A PARTICULAR PURPOSE.                                              --
--                                                                            --
--     Xilinx products are not intended for use in life support               --
--     appliances, devices, or systems. Use in such applications are          --
--     expressly prohibited.                                                  --
--                                                                            --
--     (c) Copyright 1995-2007 Xilinx, Inc.                                   --
--     All rights reserved.                                                   --
--------------------------------------------------------------------------------
-- You must compile the wrapper file adder_subtracter_virtex2p_7_0_23d84c584623d65e.vhd when simulating
-- the core, adder_subtracter_virtex2p_7_0_23d84c584623d65e. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".

-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY adder_subtracter_virtex2p_7_0_23d84c584623d65e IS
	port (
	A: IN std_logic_VECTOR(32 downto 0);
	B: IN std_logic_VECTOR(32 downto 0);
	Q: OUT std_logic_VECTOR(32 downto 0);
	CLK: IN std_logic;
	CE: IN std_logic);
END adder_subtracter_virtex2p_7_0_23d84c584623d65e;

ARCHITECTURE adder_subtracter_virtex2p_7_0_23d84c584623d65e_a OF adder_subtracter_virtex2p_7_0_23d84c584623d65e IS
-- synthesis translate_off
component wrapped_adder_subtracter_virtex2p_7_0_23d84c584623d65e
	port (
	A: IN std_logic_VECTOR(32 downto 0);
	B: IN std_logic_VECTOR(32 downto 0);
	Q: OUT std_logic_VECTOR(32 downto 0);
	CLK: IN std_logic;
	CE: IN std_logic);
end component;

-- Configuration specification 
	for all : wrapped_adder_subtracter_virtex2p_7_0_23d84c584623d65e use entity XilinxCoreLib.C_ADDSUB_V7_0(behavioral)
		generic map(
			c_has_bypass_with_cin => 0,
			c_a_type => 1,
			c_has_sclr => 0,
			c_sync_priority => 1,
			c_has_aset => 0,
			c_has_b_out => 0,
			c_has_s => 0,
			c_has_q => 1,
			c_bypass_enable => 0,
			c_b_constant => 0,
			c_has_ovfl => 0,
			c_high_bit => 32,
			c_latency => 1,
			c_sinit_val => "0",
			c_has_bypass => 0,
			c_pipe_stages => 1,
			c_has_sset => 0,
			c_has_ainit => 0,
			c_has_a_signed => 0,
			c_has_q_c_out => 0,
			c_b_type => 1,
			c_has_add => 0,
			c_has_sinit => 0,
			c_has_b_in => 0,
			c_has_b_signed => 0,
			c_bypass_low => 0,
			c_enable_rlocs => 1,
			c_b_value => "0",
			c_add_mode => 0,
			c_has_aclr => 0,
			c_out_width => 33,
			c_ainit_val => "0000",
			c_low_bit => 0,
			c_has_q_ovfl => 0,
			c_has_q_b_out => 0,
			c_has_c_out => 0,
			c_b_width => 33,
			c_a_width => 33,
			c_sync_enable => 0,
			c_has_ce => 1,
			c_has_c_in => 0);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_adder_subtracter_virtex2p_7_0_23d84c584623d65e
		port map (
			A => A,
			B => B,
			Q => Q,
			CLK => CLK,
			CE => CE);
-- synthesis translate_on

END adder_subtracter_virtex2p_7_0_23d84c584623d65e_a;


-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
package conv_pkg is
    constant simulating : boolean := false
      -- synopsys translate_off
        or true
      -- synopsys translate_on
    ;
    constant xlUnsigned : integer := 1;
    constant xlSigned : integer := 2;
    constant xlWrap : integer := 1;
    constant xlSaturate : integer := 2;
    constant xlTruncate : integer := 1;
    constant xlRound : integer := 2;
    constant xlRoundBanker : integer := 3;
    constant xlAddMode : integer := 1;
    constant xlSubMode : integer := 2;
    attribute black_box : boolean;
    attribute syn_black_box : boolean;
    attribute fpga_dont_touch: string;
    attribute box_type :  string;
    attribute keep : string;
    attribute syn_keep : boolean;
    function std_logic_vector_to_unsigned(inp : std_logic_vector) return unsigned;
    function unsigned_to_std_logic_vector(inp : unsigned) return std_logic_vector;
    function std_logic_vector_to_signed(inp : std_logic_vector) return signed;
    function signed_to_std_logic_vector(inp : signed) return std_logic_vector;
    function unsigned_to_signed(inp : unsigned) return signed;
    function signed_to_unsigned(inp : signed) return unsigned;
    function pos(inp : std_logic_vector; arith : INTEGER) return boolean;
    function all_same(inp: std_logic_vector) return boolean;
    function all_zeros(inp: std_logic_vector) return boolean;
    function is_point_five(inp: std_logic_vector) return boolean;
    function all_ones(inp: std_logic_vector) return boolean;
    function convert_type (inp : std_logic_vector; old_width, old_bin_pt,
                           old_arith, new_width, new_bin_pt, new_arith,
                           quantization, overflow : INTEGER)
        return std_logic_vector;
    function cast (inp : std_logic_vector; old_bin_pt,
                   new_width, new_bin_pt, new_arith : INTEGER)
        return std_logic_vector;
    function vec_slice (inp : std_logic_vector; upper, lower : INTEGER)
        return std_logic_vector;
    function s2u_slice (inp : signed; upper, lower : INTEGER)
        return unsigned;
    function u2u_slice (inp : unsigned; upper, lower : INTEGER)
        return unsigned;
    function s2s_cast (inp : signed; old_bin_pt,
                   new_width, new_bin_pt : INTEGER)
        return signed;
    function u2s_cast (inp : unsigned; old_bin_pt,
                   new_width, new_bin_pt : INTEGER)
        return signed;
    function s2u_cast (inp : signed; old_bin_pt,
                   new_width, new_bin_pt : INTEGER)
        return unsigned;
    function u2u_cast (inp : unsigned; old_bin_pt,
                   new_width, new_bin_pt : INTEGER)
        return unsigned;
    function u2v_cast (inp : unsigned; old_bin_pt,
                   new_width, new_bin_pt : INTEGER)
        return std_logic_vector;
    function s2v_cast (inp : signed; old_bin_pt,
                   new_width, new_bin_pt : INTEGER)
        return std_logic_vector;
    function trunc (inp : std_logic_vector; old_width, old_bin_pt, old_arith,
                    new_width, new_bin_pt, new_arith : INTEGER)
        return std_logic_vector;
    function round_towards_inf (inp : std_logic_vector; old_width, old_bin_pt,
                                old_arith, new_width, new_bin_pt,
                                new_arith : INTEGER) return std_logic_vector;
    function round_towards_even (inp : std_logic_vector; old_width, old_bin_pt,
                                old_arith, new_width, new_bin_pt,
                                new_arith : INTEGER) return std_logic_vector;
    function max_signed(width : INTEGER) return std_logic_vector;
    function min_signed(width : INTEGER) return std_logic_vector;
    function saturation_arith(inp:  std_logic_vector;  old_width, old_bin_pt,
                              old_arith, new_width, new_bin_pt, new_arith
                              : INTEGER) return std_logic_vector;
    function wrap_arith(inp:  std_logic_vector;  old_width, old_bin_pt,
                        old_arith, new_width, new_bin_pt, new_arith : INTEGER)
                        return std_logic_vector;
    function fractional_bits(a_bin_pt, b_bin_pt: INTEGER) return INTEGER;
    function integer_bits(a_width, a_bin_pt, b_width, b_bin_pt: INTEGER)
        return INTEGER;
    function sign_ext(inp : std_logic_vector; new_width : INTEGER)
        return std_logic_vector;
    function zero_ext(inp : std_logic_vector; new_width : INTEGER)
        return std_logic_vector;
    function zero_ext(inp : std_logic; new_width : INTEGER)
        return std_logic_vector;
    function extend_MSB(inp : std_logic_vector; new_width, arith : INTEGER)
        return std_logic_vector;
    function align_input(inp : std_logic_vector; old_width, delta, new_arith,
                          new_width: INTEGER)
        return std_logic_vector;
    function pad_LSB(inp : std_logic_vector; new_width: integer)
        return std_logic_vector;
    function pad_LSB(inp : std_logic_vector; new_width, arith : integer)
        return std_logic_vector;
    function max(L, R: INTEGER) return INTEGER;
    function min(L, R: INTEGER) return INTEGER;
    function "="(left,right: STRING) return boolean;
    function boolean_to_signed (inp : boolean; width: integer)
        return signed;
    function boolean_to_unsigned (inp : boolean; width: integer)
        return unsigned;
    function boolean_to_vector (inp : boolean)
        return std_logic_vector;
    function integer_to_std_logic_vector (inp : integer;  width, arith : integer)
        return std_logic_vector;
    function std_logic_vector_to_integer (inp : std_logic_vector;  arith : integer)
        return integer;
    function std_logic_to_integer(constant inp : std_logic := '0')
        return integer;
    function bin_string_element_to_std_logic_vector (inp : string;  width, index : integer)
        return std_logic_vector;
    function bin_string_to_std_logic_vector (inp : string)
        return std_logic_vector;
    function hex_string_to_std_logic_vector (inp : string; width : integer)
        return std_logic_vector;
    function makeZeroBinStr (width : integer) return STRING;
    function and_reduce(inp: std_logic_vector) return std_logic;
    -- synopsys translate_off
    function is_binary_string_invalid (inp : string)
        return boolean;
    function is_binary_string_undefined (inp : string)
        return boolean;
    function is_XorU(inp : std_logic_vector)
        return boolean;
    function to_real(inp : std_logic_vector; bin_pt : integer; arith : integer)
        return real;
    function std_logic_to_real(inp : std_logic; bin_pt : integer; arith : integer)
        return real;
    function real_to_std_logic_vector (inp : real;  width, bin_pt, arith : integer)
        return std_logic_vector;
    function real_string_to_std_logic_vector (inp : string;  width, bin_pt, arith : integer)
        return std_logic_vector;
    constant display_precision : integer := 20;
    function real_to_string (inp : real) return string;
    function valid_bin_string(inp : string) return boolean;
    function std_logic_vector_to_bin_string(inp : std_logic_vector) return string;
    function std_logic_to_bin_string(inp : std_logic) return string;
    function std_logic_vector_to_bin_string_w_point(inp : std_logic_vector; bin_pt : integer)
        return string;
    function real_to_bin_string(inp : real;  width, bin_pt, arith : integer)
        return string;
    type stdlogic_to_char_t is array(std_logic) of character;
    constant to_char : stdlogic_to_char_t := (
        'U' => 'U',
        'X' => 'X',
        '0' => '0',
        '1' => '1',
        'Z' => 'Z',
        'W' => 'W',
        'L' => 'L',
        'H' => 'H',
        '-' => '-');
    function SIGN (X: real ) return real;
    function CEIL (X : real ) return real;
    function FLOOR (X : real ) return real;
    function ROUND (X : real ) return real;
    function FMAX (X, Y : real ) return real;
    function FMIN (X, Y : real ) return real;
    -- synopsys translate_on
end conv_pkg;
package body conv_pkg is
    function std_logic_vector_to_unsigned(inp : std_logic_vector)
        return unsigned
    is
        variable vec : std_logic_vector(inp'range);
        variable result : unsigned(inp'range);
    begin
        vec := inp;
        -- synopsys translate_off
        if Is_X(vec) then
            result := (others => 'X');
            return result;
        end if;
        -- synopsys translate_on
        for i in vec'range loop
            if vec(i) = '1' then
                result(i) := '1';
            else
                result(i) := '0';
            end if;
        end loop;
        return result;
    end;
    function unsigned_to_std_logic_vector(inp : unsigned)
        return std_logic_vector
    is
        variable vec : unsigned(inp'range);
        variable result : std_logic_vector(inp'range);
    begin
        vec := inp;
        for i in vec'range loop
            if vec(i) = '1' then
                result(i) := '1';
            else
                result(i) := '0';
            end if;
        end loop;
        return result;
    end;
    function std_logic_vector_to_signed(inp : std_logic_vector)
        return signed
    is
        variable vec : std_logic_vector(inp'range);
        variable result : signed(inp'range);
    begin
        vec := inp;
        -- synopsys translate_off
        if Is_X(vec) then
            result := (others => 'X');
            return result;
        end if;
        -- synopsys translate_on
        for i in vec'range loop
            if vec(i) = '1' then
                result(i) := '1';
            else
                result(i) := '0';
            end if;
        end loop;
        return result;
    end;
    function signed_to_std_logic_vector(inp : signed)
        return std_logic_vector
    is
        variable vec : signed(inp'range);
        variable result : std_logic_vector(inp'range);
    begin
        vec := inp;
        for i in vec'range loop
            if vec(i) = '1' then
                result(i) := '1';
            else
                result(i) := '0';
            end if;
        end loop;
        return result;
    end;
    function unsigned_to_signed (inp : unsigned)
        return signed
    is
    begin
        return signed(std_logic_vector(inp));
    end;
    function signed_to_unsigned (inp : signed)
        return unsigned
    is
    begin
        return unsigned(std_logic_vector(inp));
    end;
    function pos(inp : std_logic_vector; arith : INTEGER)
        return boolean
    is
        constant width : integer := inp'length;
        variable vec : std_logic_vector(width-1 downto 0);
    begin
        vec := inp;
        if arith = xlUnsigned then
            return true;
        else
            if vec(width-1) = '0' then
                return true;
            else
                return false;
            end if;
        end if;
        return true;
    end;
    function max_signed(width : INTEGER)
        return std_logic_vector
    is
        variable ones : std_logic_vector(width-2 downto 0);
        variable result : std_logic_vector(width-1 downto 0);
    begin
        ones := (others => '1');
        result(width-1) := '0';
        result(width-2 downto 0) := ones;
        return result;
    end;
    function min_signed(width : INTEGER)
        return std_logic_vector
    is
        variable zeros : std_logic_vector(width-2 downto 0);
        variable result : std_logic_vector(width-1 downto 0);
    begin
        zeros := (others => '0');
        result(width-1) := '1';
        result(width-2 downto 0) := zeros;
        return result;
    end;
    function and_reduce(inp: std_logic_vector) return std_logic
    is
        variable result: std_logic;
        constant width : integer := inp'length;
        variable vec : std_logic_vector(width-1 downto 0);
    begin
        vec := inp;
        result := vec(0);
        if width > 1 then
            for i in 1 to width-1 loop
                result := result and vec(i);
            end loop;
        end if;
        return result;
    end;
    function all_same(inp: std_logic_vector) return boolean
    is
        variable result: boolean;
        constant width : integer := inp'length;
        variable vec : std_logic_vector(width-1 downto 0);
    begin
        vec := inp;
        result := true;
        if width > 0 then
            for i in 1 to width-1 loop
                if vec(i) /= vec(0) then
                    result := false;
                end if;
            end loop;
        end if;
        return result;
    end;
    function all_zeros(inp: std_logic_vector)
        return boolean
    is
        constant width : integer := inp'length;
        variable vec : std_logic_vector(width-1 downto 0);
        variable zero : std_logic_vector(width-1 downto 0);
        variable result : boolean;
    begin
        zero := (others => '0');
        vec := inp;
        -- synopsys translate_off
        if (is_XorU(vec)) then
            return false;
        end if;
         -- synopsys translate_on
        if (std_logic_vector_to_unsigned(vec) = std_logic_vector_to_unsigned(zero)) then
            result := true;
        else
            result := false;
        end if;
        return result;
    end;
    function is_point_five(inp: std_logic_vector)
        return boolean
    is
        constant width : integer := inp'length;
        variable vec : std_logic_vector(width-1 downto 0);
        variable result : boolean;
    begin
        vec := inp;
        -- synopsys translate_off
        if (is_XorU(vec)) then
            return false;
        end if;
         -- synopsys translate_on
        if (width > 1) then
           if ((vec(width-1) = '1') and (all_zeros(vec(width-2 downto 0)) = true)) then
               result := true;
           else
               result := false;
           end if;
        else
           if (vec(width-1) = '1') then
               result := true;
           else
               result := false;
           end if;
        end if;
        return result;
    end;
    function all_ones(inp: std_logic_vector)
        return boolean
    is
        constant width : integer := inp'length;
        variable vec : std_logic_vector(width-1 downto 0);
        variable one : std_logic_vector(width-1 downto 0);
        variable result : boolean;
    begin
        one := (others => '1');
        vec := inp;
        -- synopsys translate_off
        if (is_XorU(vec)) then
            return false;
        end if;
         -- synopsys translate_on
        if (std_logic_vector_to_unsigned(vec) = std_logic_vector_to_unsigned(one)) then
            result := true;
        else
            result := false;
        end if;
        return result;
    end;
    function full_precision_num_width(quantization, overflow, old_width,
                                      old_bin_pt, old_arith,
                                      new_width, new_bin_pt, new_arith : INTEGER)
        return integer
    is
        variable result : integer;
    begin
        result := old_width + 2;
        return result;
    end;
    function quantized_num_width(quantization, overflow, old_width, old_bin_pt,
                                 old_arith, new_width, new_bin_pt, new_arith
                                 : INTEGER)
        return integer
    is
        variable right_of_dp, left_of_dp, result : integer;
    begin
        right_of_dp := max(new_bin_pt, old_bin_pt);
        left_of_dp := max((new_width - new_bin_pt), (old_width - old_bin_pt));
        result := (old_width + 2) + (new_bin_pt - old_bin_pt);
        return result;
    end;
    function convert_type (inp : std_logic_vector; old_width, old_bin_pt,
                           old_arith, new_width, new_bin_pt, new_arith,
                           quantization, overflow : INTEGER)
        return std_logic_vector
    is
        constant fp_width : integer :=
            full_precision_num_width(quantization, overflow, old_width,
                                     old_bin_pt, old_arith, new_width,
                                     new_bin_pt, new_arith);
        constant fp_bin_pt : integer := old_bin_pt;
        constant fp_arith : integer := old_arith;
        variable full_precision_result : std_logic_vector(fp_width-1 downto 0);
        constant q_width : integer :=
            quantized_num_width(quantization, overflow, old_width, old_bin_pt,
                                old_arith, new_width, new_bin_pt, new_arith);
        constant q_bin_pt : integer := new_bin_pt;
        constant q_arith : integer := old_arith;
        variable quantized_result : std_logic_vector(q_width-1 downto 0);
        variable result : std_logic_vector(new_width-1 downto 0);
    begin
        result := (others => '0');
        full_precision_result := cast(inp, old_bin_pt, fp_width, fp_bin_pt,
                                      fp_arith);
        if (quantization = xlRound) then
            quantized_result := round_towards_inf(full_precision_result,
                                                  fp_width, fp_bin_pt,
                                                  fp_arith, q_width, q_bin_pt,
                                                  q_arith);
        elsif (quantization = xlRoundBanker) then
            quantized_result := round_towards_even(full_precision_result,
                                                  fp_width, fp_bin_pt,
                                                  fp_arith, q_width, q_bin_pt,
                                                  q_arith);
        else
            quantized_result := trunc(full_precision_result, fp_width, fp_bin_pt,
                                      fp_arith, q_width, q_bin_pt, q_arith);
        end if;
        if (overflow = xlSaturate) then
            result := saturation_arith(quantized_result, q_width, q_bin_pt,
                                       q_arith, new_width, new_bin_pt, new_arith);
        else
             result := wrap_arith(quantized_result, q_width, q_bin_pt, q_arith,
                                  new_width, new_bin_pt, new_arith);
        end if;
        return result;
    end;
    function cast (inp : std_logic_vector; old_bin_pt, new_width,
                   new_bin_pt, new_arith : INTEGER)
        return std_logic_vector
    is
        constant old_width : integer := inp'length;
        constant left_of_dp : integer := (new_width - new_bin_pt)
                                         - (old_width - old_bin_pt);
        constant right_of_dp : integer := (new_bin_pt - old_bin_pt);
        variable vec : std_logic_vector(old_width-1 downto 0);
        variable result : std_logic_vector(new_width-1 downto 0);
        variable j   : integer;
    begin
        vec := inp;
        for i in new_width-1 downto 0 loop
            j := i - right_of_dp;
            if ( j > old_width-1) then
                if (new_arith = xlUnsigned) then
                    result(i) := '0';
                else
                    result(i) := vec(old_width-1);
                end if;
            elsif ( j >= 0) then
                result(i) := vec(j);
            else
                result(i) := '0';
            end if;
        end loop;
        return result;
    end;
    function vec_slice (inp : std_logic_vector; upper, lower : INTEGER)
      return std_logic_vector
    is
    begin
        return inp(upper downto lower);
    end;
    function s2u_slice (inp : signed; upper, lower : INTEGER)
      return unsigned
    is
    begin
        return unsigned(vec_slice(std_logic_vector(inp), upper, lower));
    end;
    function u2u_slice (inp : unsigned; upper, lower : INTEGER)
      return unsigned
    is
    begin
        return unsigned(vec_slice(std_logic_vector(inp), upper, lower));
    end;
    function s2s_cast (inp : signed; old_bin_pt, new_width, new_bin_pt : INTEGER)
        return signed
    is
    begin
        return signed(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned));
    end;
    function s2u_cast (inp : signed; old_bin_pt, new_width,
                   new_bin_pt : INTEGER)
        return unsigned
    is
    begin
        return unsigned(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned));
    end;
    function u2s_cast (inp : unsigned; old_bin_pt, new_width,
                   new_bin_pt : INTEGER)
        return signed
    is
    begin
        return signed(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned));
    end;
    function u2u_cast (inp : unsigned; old_bin_pt, new_width,
                   new_bin_pt : INTEGER)
        return unsigned
    is
    begin
        return unsigned(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned));
    end;
    function u2v_cast (inp : unsigned; old_bin_pt, new_width,
                   new_bin_pt : INTEGER)
        return std_logic_vector
    is
    begin
        return cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned);
    end;
    function s2v_cast (inp : signed; old_bin_pt, new_width,
                   new_bin_pt : INTEGER)
        return std_logic_vector
    is
    begin
        return cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned);
    end;
    function boolean_to_signed (inp : boolean; width : integer)
        return signed
    is
        variable result : signed(width - 1 downto 0);
    begin
        result := (others => '0');
        if inp then
          result(0) := '1';
        else
          result(0) := '0';
        end if;
        return result;
    end;
    function boolean_to_unsigned (inp : boolean; width : integer)
        return unsigned
    is
        variable result : unsigned(width - 1 downto 0);
    begin
        result := (others => '0');
        if inp then
          result(0) := '1';
        else
          result(0) := '0';
        end if;
        return result;
    end;
    function boolean_to_vector (inp : boolean)
        return std_logic_vector
    is
        variable result : std_logic_vector(1 - 1 downto 0);
    begin
        result := (others => '0');
        if inp then
          result(0) := '1';
        else
          result(0) := '0';
        end if;
        return result;
    end;
    function trunc (inp : std_logic_vector; old_width, old_bin_pt, old_arith,
                                new_width, new_bin_pt, new_arith : INTEGER)
        return std_logic_vector
    is
        constant right_of_dp : integer := (old_bin_pt - new_bin_pt);
        variable vec : std_logic_vector(old_width-1 downto 0);
        variable result : std_logic_vector(new_width-1 downto 0);
    begin
        vec := inp;
        if right_of_dp >= 0 then
            if new_arith = xlUnsigned then
                result := zero_ext(vec(old_width-1 downto right_of_dp), new_width);
            else
                result := sign_ext(vec(old_width-1 downto right_of_dp), new_width);
            end if;
        else
            if new_arith = xlUnsigned then
                result := zero_ext(pad_LSB(vec, old_width +
                                           abs(right_of_dp)), new_width);
            else
                result := sign_ext(pad_LSB(vec, old_width +
                                           abs(right_of_dp)), new_width);
            end if;
        end if;
        return result;
    end;
    function round_towards_inf (inp : std_logic_vector; old_width, old_bin_pt,
                                old_arith, new_width, new_bin_pt, new_arith
                                : INTEGER)
        return std_logic_vector
    is
        constant right_of_dp : integer := (old_bin_pt - new_bin_pt);
        constant expected_new_width : integer :=  old_width - right_of_dp  + 1;
        variable vec : std_logic_vector(old_width-1 downto 0);
        variable one_or_zero : std_logic_vector(new_width-1 downto 0);
        variable truncated_val : std_logic_vector(new_width-1 downto 0);
        variable result : std_logic_vector(new_width-1 downto 0);
    begin
        vec := inp;
        if right_of_dp >= 0 then
            if new_arith = xlUnsigned then
                truncated_val := zero_ext(vec(old_width-1 downto right_of_dp),
                                          new_width);
            else
                truncated_val := sign_ext(vec(old_width-1 downto right_of_dp),
                                          new_width);
            end if;
        else
            if new_arith = xlUnsigned then
                truncated_val := zero_ext(pad_LSB(vec, old_width +
                                                  abs(right_of_dp)), new_width);
            else
                truncated_val := sign_ext(pad_LSB(vec, old_width +
                                                  abs(right_of_dp)), new_width);
            end if;
        end if;
        one_or_zero := (others => '0');
        if (new_arith = xlSigned) then
            if (vec(old_width-1) = '0') then
                one_or_zero(0) := '1';
            end if;
            if (right_of_dp >= 2) and (right_of_dp <= old_width) then
                if (all_zeros(vec(right_of_dp-2 downto 0)) = false) then
                    one_or_zero(0) := '1';
                end if;
            end if;
            if (right_of_dp >= 1) and (right_of_dp <= old_width) then
                if vec(right_of_dp-1) = '0' then
                    one_or_zero(0) := '0';
                end if;
            else
                one_or_zero(0) := '0';
            end if;
        else
            if (right_of_dp >= 1) and (right_of_dp <= old_width) then
                one_or_zero(0) :=  vec(right_of_dp-1);
            end if;
        end if;
        if new_arith = xlSigned then
            result := signed_to_std_logic_vector(std_logic_vector_to_signed(truncated_val) +
                                                 std_logic_vector_to_signed(one_or_zero));
        else
            result := unsigned_to_std_logic_vector(std_logic_vector_to_unsigned(truncated_val) +
                                                  std_logic_vector_to_unsigned(one_or_zero));
        end if;
        return result;
    end;
    function round_towards_even (inp : std_logic_vector; old_width, old_bin_pt,
                                old_arith, new_width, new_bin_pt, new_arith
                                : INTEGER)
        return std_logic_vector
    is
        constant right_of_dp : integer := (old_bin_pt - new_bin_pt);
        constant expected_new_width : integer :=  old_width - right_of_dp  + 1;
        variable vec : std_logic_vector(old_width-1 downto 0);
        variable one_or_zero : std_logic_vector(new_width-1 downto 0);
        variable truncated_val : std_logic_vector(new_width-1 downto 0);
        variable result : std_logic_vector(new_width-1 downto 0);
    begin
        vec := inp;
        if right_of_dp >= 0 then
            if new_arith = xlUnsigned then
                truncated_val := zero_ext(vec(old_width-1 downto right_of_dp),
                                          new_width);
            else
                truncated_val := sign_ext(vec(old_width-1 downto right_of_dp),
                                          new_width);
            end if;
        else
            if new_arith = xlUnsigned then
                truncated_val := zero_ext(pad_LSB(vec, old_width +
                                                  abs(right_of_dp)), new_width);
            else
                truncated_val := sign_ext(pad_LSB(vec, old_width +
                                                  abs(right_of_dp)), new_width);
            end if;
        end if;
        one_or_zero := (others => '0');
        if (right_of_dp >= 1) and (right_of_dp <= old_width) then
            if (is_point_five(vec(right_of_dp-1 downto 0)) = false) then
                one_or_zero(0) :=  vec(right_of_dp-1);
            else
                one_or_zero(0) :=  vec(right_of_dp);
            end if;
        end if;
        if new_arith = xlSigned then
            result := signed_to_std_logic_vector(std_logic_vector_to_signed(truncated_val) +
                                                 std_logic_vector_to_signed(one_or_zero));
        else
            result := unsigned_to_std_logic_vector(std_logic_vector_to_unsigned(truncated_val) +
                                                  std_logic_vector_to_unsigned(one_or_zero));
        end if;
        return result;
    end;
    function saturation_arith(inp:  std_logic_vector;  old_width, old_bin_pt,
                              old_arith, new_width, new_bin_pt, new_arith
                              : INTEGER)
        return std_logic_vector
    is
        constant left_of_dp : integer := (old_width - old_bin_pt) -
                                         (new_width - new_bin_pt);
        variable vec : std_logic_vector(old_width-1 downto 0);
        variable result : std_logic_vector(new_width-1 downto 0);
        variable overflow : boolean;
    begin
        vec := inp;
        overflow := true;
        result := (others => '0');
        if (new_width >= old_width) then
            overflow := false;
        end if;
        if ((old_arith = xlSigned and new_arith = xlSigned) and (old_width > new_width)) then
            if all_same(vec(old_width-1 downto new_width-1)) then
                overflow := false;
            end if;
        end if;
        if (old_arith = xlSigned and new_arith = xlUnsigned) then
            if (old_width > new_width) then
                if all_zeros(vec(old_width-1 downto new_width)) then
                    overflow := false;
                end if;
            else
                if (old_width = new_width) then
                    if (vec(new_width-1) = '0') then
                        overflow := false;
                    end if;
                end if;
            end if;
        end if;
        if (old_arith = xlUnsigned and new_arith = xlUnsigned) then
            if (old_width > new_width) then
                if all_zeros(vec(old_width-1 downto new_width)) then
                    overflow := false;
                end if;
            else
                if (old_width = new_width) then
                    overflow := false;
                end if;
            end if;
        end if;
        if ((old_arith = xlUnsigned and new_arith = xlSigned) and (old_width > new_width)) then
            if all_same(vec(old_width-1 downto new_width-1)) then
                overflow := false;
            end if;
        end if;
        if overflow then
            if new_arith = xlSigned then
                if vec(old_width-1) = '0' then
                    result := max_signed(new_width);
                else
                    result := min_signed(new_width);
                end if;
            else
                if ((old_arith = xlSigned) and vec(old_width-1) = '1') then
                    result := (others => '0');
                else
                    result := (others => '1');
                end if;
            end if;
        else
            if (old_arith = xlSigned) and (new_arith = xlUnsigned) then
                if (vec(old_width-1) = '1') then
                    vec := (others => '0');
                end if;
            end if;
            if new_width <= old_width then
                result := vec(new_width-1 downto 0);
            else
                if new_arith = xlUnsigned then
                    result := zero_ext(vec, new_width);
                else
                    result := sign_ext(vec, new_width);
                end if;
            end if;
        end if;
        return result;
    end;
   function wrap_arith(inp:  std_logic_vector;  old_width, old_bin_pt,
                       old_arith, new_width, new_bin_pt, new_arith : INTEGER)
        return std_logic_vector
    is
        variable result : std_logic_vector(new_width-1 downto 0);
        variable result_arith : integer;
    begin
        if (old_arith = xlSigned) and (new_arith = xlUnsigned) then
            result_arith := xlSigned;
        end if;
        result := cast(inp, old_bin_pt, new_width, new_bin_pt, result_arith);
        return result;
    end;
    function fractional_bits(a_bin_pt, b_bin_pt: INTEGER) return INTEGER is
    begin
        return max(a_bin_pt, b_bin_pt);
    end;
    function integer_bits(a_width, a_bin_pt, b_width, b_bin_pt: INTEGER)
        return INTEGER is
    begin
        return  max(a_width - a_bin_pt, b_width - b_bin_pt);
    end;
    function pad_LSB(inp : std_logic_vector; new_width: integer)
        return STD_LOGIC_VECTOR
    is
        constant orig_width : integer := inp'length;
        variable vec : std_logic_vector(orig_width-1 downto 0);
        variable result : std_logic_vector(new_width-1 downto 0);
        variable pos : integer;
        constant pad_pos : integer := new_width - orig_width - 1;
    begin
        vec := inp;
        pos := new_width-1;
        if (new_width >= orig_width) then
            for i in orig_width-1 downto 0 loop
                result(pos) := vec(i);
                pos := pos - 1;
            end loop;
            if pad_pos >= 0 then
                for i in pad_pos downto 0 loop
                    result(i) := '0';
                end loop;
            end if;
        end if;
        return result;
    end;
    function sign_ext(inp : std_logic_vector; new_width : INTEGER)
        return std_logic_vector
    is
        constant old_width : integer := inp'length;
        variable vec : std_logic_vector(old_width-1 downto 0);
        variable result : std_logic_vector(new_width-1 downto 0);
    begin
        vec := inp;
        if new_width >= old_width then
            result(old_width-1 downto 0) := vec;
            if new_width-1 >= old_width then
                for i in new_width-1 downto old_width loop
                    result(i) := vec(old_width-1);
                end loop;
            end if;
        else
            result(new_width-1 downto 0) := vec(new_width-1 downto 0);
        end if;
        return result;
    end;
    function zero_ext(inp : std_logic_vector; new_width : INTEGER)
        return std_logic_vector
    is
        constant old_width : integer := inp'length;
        variable vec : std_logic_vector(old_width-1 downto 0);
        variable result : std_logic_vector(new_width-1 downto 0);
    begin
        vec := inp;
        if new_width >= old_width then
            result(old_width-1 downto 0) := vec;
            if new_width-1 >= old_width then
                for i in new_width-1 downto old_width loop
                    result(i) := '0';
                end loop;
            end if;
        else
            result(new_width-1 downto 0) := vec(new_width-1 downto 0);
        end if;
        return result;
    end;
    function zero_ext(inp : std_logic; new_width : INTEGER)
        return std_logic_vector
    is
        variable result : std_logic_vector(new_width-1 downto 0);
    begin
        result(0) := inp;
        for i in new_width-1 downto 1 loop
            result(i) := '0';
        end loop;
        return result;
    end;
    function extend_MSB(inp : std_logic_vector; new_width, arith : INTEGER)
        return std_logic_vector
    is
        constant orig_width : integer := inp'length;
        variable vec : std_logic_vector(orig_width-1 downto 0);
        variable result : std_logic_vector(new_width-1 downto 0);
    begin
        vec := inp;
        if arith = xlUnsigned then
            result := zero_ext(vec, new_width);
        else
            result := sign_ext(vec, new_width);
        end if;
        return result;
    end;
    function pad_LSB(inp : std_logic_vector; new_width, arith: integer)
        return STD_LOGIC_VECTOR
    is
        constant orig_width : integer := inp'length;
        variable vec : std_logic_vector(orig_width-1 downto 0);
        variable result : std_logic_vector(new_width-1 downto 0);
        variable pos : integer;
    begin
        vec := inp;
        pos := new_width-1;
        if (arith = xlUnsigned) then
            result(pos) := '0';
            pos := pos - 1;
        else
            result(pos) := vec(orig_width-1);
            pos := pos - 1;
        end if;
        if (new_width >= orig_width) then
            for i in orig_width-1 downto 0 loop
                result(pos) := vec(i);
                pos := pos - 1;
            end loop;
            if pos >= 0 then
                for i in pos downto 0 loop
                    result(i) := '0';
                end loop;
            end if;
        end if;
        return result;
    end;
    function align_input(inp : std_logic_vector; old_width, delta, new_arith,
                         new_width: INTEGER)
        return std_logic_vector
    is
        variable vec : std_logic_vector(old_width-1 downto 0);
        variable padded_inp : std_logic_vector((old_width + delta)-1  downto 0);
        variable result : std_logic_vector(new_width-1 downto 0);
    begin
        vec := inp;
        if delta > 0 then
            padded_inp := pad_LSB(vec, old_width+delta);
            result := extend_MSB(padded_inp, new_width, new_arith);
        else
            result := extend_MSB(vec, new_width, new_arith);
        end if;
        return result;
    end;
    function max(L, R: INTEGER) return INTEGER is
    begin
        if L > R then
            return L;
        else
            return R;
        end if;
    end;
    function min(L, R: INTEGER) return INTEGER is
    begin
        if L < R then
            return L;
        else
            return R;
        end if;
    end;
    function "="(left,right: STRING) return boolean is
    begin
        if (left'length /= right'length) then
            return false;
        else
            test : for i in 1 to left'length loop
                if left(i) /= right(i) then
                    return false;
                end if;
            end loop test;
            return true;
        end if;
    end;
    -- synopsys translate_off
    function is_binary_string_invalid (inp : string)
        return boolean
    is
        variable vec : string(1 to inp'length);
        variable result : boolean;
    begin
        vec := inp;
        result := false;
        for i in 1 to vec'length loop
            if ( vec(i) = 'X' ) then
                result := true;
            end if;
        end loop;
        return result;
    end;
    function is_binary_string_undefined (inp : string)
        return boolean
    is
        variable vec : string(1 to inp'length);
        variable result : boolean;
    begin
        vec := inp;
        result := false;
        for i in 1 to vec'length loop
            if ( vec(i) = 'U' ) then
                result := true;
            end if;
        end loop;
        return result;
    end;
    function is_XorU(inp : std_logic_vector)
        return boolean
    is
        constant width : integer := inp'length;
        variable vec : std_logic_vector(width-1 downto 0);
        variable result : boolean;
    begin
        vec := inp;
        result := false;
        for i in 0 to width-1 loop
            if (vec(i) = 'U') or (vec(i) = 'X') then
                result := true;
            end if;
        end loop;
        return result;
    end;
    function to_real(inp : std_logic_vector; bin_pt : integer; arith : integer)
        return real
    is
        variable  vec : std_logic_vector(inp'length-1 downto 0);
        variable result, shift_val, undefined_real : real;
        variable neg_num : boolean;
    begin
        vec := inp;
        result := 0.0;
        neg_num := false;
        if vec(inp'length-1) = '1' then
            neg_num := true;
        end if;
        for i in 0 to inp'length-1 loop
            if  vec(i) = 'U' or vec(i) = 'X' then
                return undefined_real;
            end if;
            if arith = xlSigned then
                if neg_num then
                    if vec(i) = '0' then
                        result := result + 2.0**i;
                    end if;
                else
                    if vec(i) = '1' then
                        result := result + 2.0**i;
                    end if;
                end if;
            else
                if vec(i) = '1' then
                    result := result + 2.0**i;
                end if;
            end if;
        end loop;
        if arith = xlSigned then
            if neg_num then
                result := result + 1.0;
                result := result * (-1.0);
            end if;
        end if;
        shift_val := 2.0**(-1*bin_pt);
        result := result * shift_val;
        return result;
    end;
    function std_logic_to_real(inp : std_logic; bin_pt : integer; arith : integer)
        return real
    is
        variable result : real := 0.0;
    begin
        if inp = '1' then
            result := 1.0;
        end if;
        if arith = xlSigned then
            assert false
                report "It doesn't make sense to convert a 1 bit number to a signed real.";
        end if;
        return result;
    end;
    -- synopsys translate_on
    function integer_to_std_logic_vector (inp : integer;  width, arith : integer)
        return std_logic_vector
    is
        variable result : std_logic_vector(width-1 downto 0);
        variable unsigned_val : unsigned(width-1 downto 0);
        variable signed_val : signed(width-1 downto 0);
    begin
        if (arith = xlSigned) then
            signed_val := to_signed(inp, width);
            result := signed_to_std_logic_vector(signed_val);
        else
            unsigned_val := to_unsigned(inp, width);
            result := unsigned_to_std_logic_vector(unsigned_val);
        end if;
        return result;
    end;
    function std_logic_vector_to_integer (inp : std_logic_vector;  arith : integer)
        return integer
    is
        constant width : integer := inp'length;
        variable unsigned_val : unsigned(width-1 downto 0);
        variable signed_val : signed(width-1 downto 0);
        variable result : integer;
    begin
        if (arith = xlSigned) then
            signed_val := std_logic_vector_to_signed(inp);
            result := to_integer(signed_val);
        else
            unsigned_val := std_logic_vector_to_unsigned(inp);
            result := to_integer(unsigned_val);
        end if;
        return result;
    end;
    function std_logic_to_integer(constant inp : std_logic := '0')
        return integer
    is
    begin
        if inp = '1' then
            return 1;
        else
            return 0;
        end if;
    end;
    function makeZeroBinStr (width : integer) return STRING is
        variable result : string(1 to width+3);
    begin
        result(1) := '0';
        result(2) := 'b';
        for i in 3 to width+2 loop
            result(i) := '0';
        end loop;
        result(width+3) := '.';
        return result;
    end;
    -- synopsys translate_off
    function real_string_to_std_logic_vector (inp : string;  width, bin_pt, arith : integer)
        return std_logic_vector
    is
        variable result : std_logic_vector(width-1 downto 0);
    begin
        result := (others => '0');
        return result;
    end;
    function real_to_std_logic_vector (inp : real;  width, bin_pt, arith : integer)
        return std_logic_vector
    is
        variable real_val : real;
        variable int_val : integer;
        variable result : std_logic_vector(width-1 downto 0) := (others => '0');
        variable unsigned_val : unsigned(width-1 downto 0) := (others => '0');
        variable signed_val : signed(width-1 downto 0) := (others => '0');
    begin
        real_val := inp;
        int_val := integer(real_val * 2.0**(bin_pt));
        if (arith = xlSigned) then
            signed_val := to_signed(int_val, width);
            result := signed_to_std_logic_vector(signed_val);
        else
            unsigned_val := to_unsigned(int_val, width);
            result := unsigned_to_std_logic_vector(unsigned_val);
        end if;
        return result;
    end;
    -- synopsys translate_on
    function valid_bin_string (inp : string)
        return boolean
    is
        variable vec : string(1 to inp'length);
    begin
        vec := inp;
        if (vec(1) = '0' and vec(2) = 'b') then
            return true;
        else
            return false;
        end if;
    end;
    function hex_string_to_std_logic_vector(inp: string; width : integer)
        return std_logic_vector is
        constant strlen       : integer := inp'LENGTH;
        variable result       : std_logic_vector(width-1 downto 0);
        variable bitval       : std_logic_vector((strlen*4)-1 downto 0);
        variable posn         : integer;
        variable ch           : character;
        variable vec          : string(1 to strlen);
    begin
        vec := inp;
        result := (others => '0');
        posn := (strlen*4)-1;
        for i in 1 to strlen loop
            ch := vec(i);
            case ch is
                when '0' => bitval(posn downto posn-3) := "0000";
                when '1' => bitval(posn downto posn-3) := "0001";
                when '2' => bitval(posn downto posn-3) := "0010";
                when '3' => bitval(posn downto posn-3) := "0011";
                when '4' => bitval(posn downto posn-3) := "0100";
                when '5' => bitval(posn downto posn-3) := "0101";
                when '6' => bitval(posn downto posn-3) := "0110";
                when '7' => bitval(posn downto posn-3) := "0111";
                when '8' => bitval(posn downto posn-3) := "1000";
                when '9' => bitval(posn downto posn-3) := "1001";
                when 'A' | 'a' => bitval(posn downto posn-3) := "1010";
                when 'B' | 'b' => bitval(posn downto posn-3) := "1011";
                when 'C' | 'c' => bitval(posn downto posn-3) := "1100";
                when 'D' | 'd' => bitval(posn downto posn-3) := "1101";
                when 'E' | 'e' => bitval(posn downto posn-3) := "1110";
                when 'F' | 'f' => bitval(posn downto posn-3) := "1111";
                when others => bitval(posn downto posn-3) := "XXXX";
                               -- synopsys translate_off
                               ASSERT false
                                   REPORT "Invalid hex value" SEVERITY ERROR;
                               -- synopsys translate_on
            end case;
            posn := posn - 4;
        end loop;
        if (width <= strlen*4) then
            result :=  bitval(width-1 downto 0);
        else
            result((strlen*4)-1 downto 0) := bitval;
        end if;
        return result;
    end;
    function bin_string_to_std_logic_vector (inp : string)
        return std_logic_vector
    is
        variable pos : integer;
        variable vec : string(1 to inp'length);
        variable result : std_logic_vector(inp'length-1 downto 0);
    begin
        vec := inp;
        pos := inp'length-1;
        result := (others => '0');
        for i in 1 to vec'length loop
            -- synopsys translate_off
            if (pos < 0) and (vec(i) = '0' or vec(i) = '1' or vec(i) = 'X' or vec(i) = 'U')  then
                assert false
                    report "Input string is larger than output std_logic_vector. Truncating output.";
                return result;
            end if;
            -- synopsys translate_on
            if vec(i) = '0' then
                result(pos) := '0';
                pos := pos - 1;
            end if;
            if vec(i) = '1' then
                result(pos) := '1';
                pos := pos - 1;
            end if;
            -- synopsys translate_off
            if (vec(i) = 'X' or vec(i) = 'U') then
                result(pos) := 'U';
                pos := pos - 1;
            end if;
            -- synopsys translate_on
        end loop;
        return result;
    end;
    function bin_string_element_to_std_logic_vector (inp : string;  width, index : integer)
        return std_logic_vector
    is
        constant str_width : integer := width + 4;
        constant inp_len : integer := inp'length;
        constant num_elements : integer := (inp_len + 1)/str_width;
        constant reverse_index : integer := (num_elements-1) - index;
        variable left_pos : integer;
        variable right_pos : integer;
        variable vec : string(1 to inp'length);
        variable result : std_logic_vector(width-1 downto 0);
    begin
        vec := inp;
        result := (others => '0');
        if (reverse_index = 0) and (reverse_index < num_elements) and (inp_len-3 >= width) then
            left_pos := 1;
            right_pos := width + 3;
            result := bin_string_to_std_logic_vector(vec(left_pos to right_pos));
        end if;
        if (reverse_index > 0) and (reverse_index < num_elements) and (inp_len-3 >= width) then
            left_pos := (reverse_index * str_width) + 1;
            right_pos := left_pos + width + 2;
            result := bin_string_to_std_logic_vector(vec(left_pos to right_pos));
        end if;
        return result;
    end;
   -- synopsys translate_off
    function std_logic_vector_to_bin_string(inp : std_logic_vector)
        return string
    is
        variable vec : std_logic_vector(1 to inp'length);
        variable result : string(vec'range);
    begin
        vec := inp;
        for i in vec'range loop
            result(i) := to_char(vec(i));
        end loop;
        return result;
    end;
    function std_logic_to_bin_string(inp : std_logic)
        return string
    is
        variable result : string(1 to 3);
    begin
        result(1) := '0';
        result(2) := 'b';
        result(3) := to_char(inp);
        return result;
    end;
    function std_logic_vector_to_bin_string_w_point(inp : std_logic_vector; bin_pt : integer)
        return string
    is
        variable width : integer := inp'length;
        variable vec : std_logic_vector(width-1 downto 0);
        variable str_pos : integer;
        variable result : string(1 to width+3);
    begin
        vec := inp;
        str_pos := 1;
        result(str_pos) := '0';
        str_pos := 2;
        result(str_pos) := 'b';
        str_pos := 3;
        for i in width-1 downto 0  loop
            if (((width+3) - bin_pt) = str_pos) then
                result(str_pos) := '.';
                str_pos := str_pos + 1;
            end if;
            result(str_pos) := to_char(vec(i));
            str_pos := str_pos + 1;
        end loop;
        if (bin_pt = 0) then
            result(str_pos) := '.';
        end if;
        return result;
    end;
    function real_to_bin_string(inp : real;  width, bin_pt, arith : integer)
        return string
    is
        variable result : string(1 to width);
        variable vec : std_logic_vector(width-1 downto 0);
    begin
        vec := real_to_std_logic_vector(inp, width, bin_pt, arith);
        result := std_logic_vector_to_bin_string(vec);
        return result;
    end;
    function real_to_string (inp : real) return string
    is
        variable result : string(1 to display_precision) := (others => ' ');
    begin
        result(real'image(inp)'range) := real'image(inp);
        return result;
    end;
    function SIGN (X: real ) return real is
    begin
           if  ( X > 0.0 )  then
                return 1.0;
           elsif ( X < 0.0 )  then
                return -1.0;
           else
                return 0.0;
           end if;
    end SIGN;
   function CEIL (X : real ) return real is
         variable large: real  := 1073741824.0;
         type long is range -1073741824 to 1073741824;
         variable rd: real;
      begin
         if abs( X) >= large then
            return X;
         else
            rd := real ( long( X));
            if X > 0.0 then
                if rd >= X then
                        return rd;
                else
                        return rd + 1.0;
                end if;
            elsif  X = 0.0  then
                        return 0.0;
            else
                if rd <= X then
                        return rd;
                else
                        return rd - 1.0;
                end if;
            end if;
         end if;
      end CEIL;
    function FLOOR (X : real ) return real is
         variable large: real  := 1073741824.0;
         type long is range -1073741824 to 1073741824;
         variable rd: real;
      begin
         if abs( X ) >= large then
                return X;
         else
                rd := real ( long( X));
                if X > 0.0 then
                        if rd <= X then
                                return rd;
                        else
                                return rd - 1.0;
                        end if;
                elsif  X = 0.0  then
                        return 0.0;
                else
                        if rd >= X then
                                return rd;
                        else
                                return rd + 1.0;
                        end if;
                end if;
         end if;
      end FLOOR;
    function ROUND (X : real ) return real is
    begin
           if  X > 0.0  then
                return FLOOR(X + 0.5);
           elsif  X < 0.0  then
                return CEIL( X - 0.5);
           else
                return 0.0;
           end if;
    end ROUND;
    function FMAX (X, Y : real ) return real is
    begin
        if X > Y then
           return X;
        else
           return Y;
        end if;
    end FMAX;
    function FMIN (X, Y : real ) return real is
    begin
        if X < Y then
           return X;
        else
           return Y;
        end if;
    end FMIN;
    -- synopsys translate_on
end conv_pkg;
library IEEE;
use IEEE.std_logic_1164.all;
package clock_pkg is
-- synopsys translate_off
   signal int_clk : std_logic;
-- synopsys translate_on
end clock_pkg;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
-- synopsys translate_off
library unisim;
use unisim.vcomponents.all;
-- synopsys translate_on
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity srl17e is
    generic (width : integer:=16;
             latency : integer :=8);
    port (clk   : in std_logic;
          ce    : in std_logic;
          d     : in std_logic_vector(width-1 downto 0);
          q     : out std_logic_vector(width-1 downto 0));
end srl17e;
architecture structural of srl17e is
    component SRL16E
        port (D   : in STD_ULOGIC;
              CE  : in STD_ULOGIC;
              CLK : in STD_ULOGIC;
              A0  : in STD_ULOGIC;
              A1  : in STD_ULOGIC;
              A2  : in STD_ULOGIC;
              A3  : in STD_ULOGIC;
              Q   : out STD_ULOGIC);
    end component;
    attribute syn_black_box of SRL16E : component is true;
    attribute fpga_dont_touch of SRL16E : component is "true";
    component FDE
        port(
            Q  :        out   STD_ULOGIC;
            D  :        in    STD_ULOGIC;
            C  :        in    STD_ULOGIC;
            CE :        in    STD_ULOGIC);
    end component;
    attribute syn_black_box of FDE : component is true;
    attribute fpga_dont_touch of FDE : component is "true";
    constant a : std_logic_vector(4 downto 0) :=
        integer_to_std_logic_vector(latency-2,5,xlSigned);
    signal d_delayed : std_logic_vector(width-1 downto 0);
    signal srl16_out : std_logic_vector(width-1 downto 0);
begin
    d_delayed <= d after 200 ps;
    reg_array : for i in 0 to width-1 generate
        srl16_used: if latency > 1 generate
            u1 : srl16e port map(clk => clk,
                                 d => d_delayed(i),
                                 q => srl16_out(i),
                                 ce => ce,
                                 a0 => a(0),
                                 a1 => a(1),
                                 a2 => a(2),
                                 a3 => a(3));
        end generate;
        srl16_not_used: if latency <= 1 generate
            srl16_out(i) <= d_delayed(i);
        end generate;
        fde_used: if latency /= 0  generate
            u2 : fde port map(c => clk,
                              d => srl16_out(i),
                              q => q(i),
                              ce => ce);
        end generate;
        fde_not_used: if latency = 0  generate
            q(i) <= srl16_out(i);
        end generate;
    end generate;
 end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity synth_reg is
    generic (width           : integer := 8;
             latency         : integer := 1);
    port (i       : in std_logic_vector(width-1 downto 0);
          ce      : in std_logic;
          clr     : in std_logic;
          clk     : in std_logic;
          o       : out std_logic_vector(width-1 downto 0));
end synth_reg;
architecture structural of synth_reg is
    component srl17e
        generic (width : integer:=16;
                 latency : integer :=8);
        port (clk : in std_logic;
              ce  : in std_logic;
              d   : in std_logic_vector(width-1 downto 0);
              q   : out std_logic_vector(width-1 downto 0));
    end component;
    function calc_num_srl17es (latency : integer)
        return integer
    is
        variable remaining_latency : integer;
        variable result : integer;
    begin
        result := latency / 17;
        remaining_latency := latency - (result * 17);
        if (remaining_latency /= 0) then
            result := result + 1;
        end if;
        return result;
    end;
    constant complete_num_srl17es : integer := latency / 17;
    constant num_srl17es : integer := calc_num_srl17es(latency);
    constant remaining_latency : integer := latency - (complete_num_srl17es * 17);
    type register_array is array (num_srl17es downto 0) of
        std_logic_vector(width-1 downto 0);
    signal z : register_array;
begin
    z(0) <= i;
    complete_ones : if complete_num_srl17es > 0 generate
        srl17e_array: for i in 0 to complete_num_srl17es-1 generate
            delay_comp : srl17e
                generic map (width => width,
                             latency => 17)
                port map (clk => clk,
                          ce  => ce,
                          d       => z(i),
                          q       => z(i+1));
        end generate;
    end generate;
    partial_one : if remaining_latency > 0 generate
        last_srl17e : srl17e
            generic map (width => width,
                         latency => remaining_latency)
            port map (clk => clk,
                      ce  => ce,
                      d   => z(num_srl17es-1),
                      q   => z(num_srl17es));
    end generate;
    o <= z(num_srl17es);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity synth_reg_reg is
    generic (width           : integer := 8;
             latency         : integer := 1);
    port (i       : in std_logic_vector(width-1 downto 0);
          ce      : in std_logic;
          clr     : in std_logic;
          clk     : in std_logic;
          o       : out std_logic_vector(width-1 downto 0));
end synth_reg_reg;
architecture behav of synth_reg_reg is
  type reg_array_type is array (latency-1 downto 0) of std_logic_vector(width -1 downto 0);
  signal reg_bank : reg_array_type := (others => (others => '0'));
  signal reg_bank_in : reg_array_type := (others => (others => '0'));
  attribute syn_allow_retiming : boolean;
  attribute syn_srlstyle : string;
  attribute syn_allow_retiming of reg_bank : signal is true;
  attribute syn_allow_retiming of reg_bank_in : signal is true;
  attribute syn_srlstyle of reg_bank : signal is "registers";
  attribute syn_srlstyle of reg_bank_in : signal is "registers";
begin
  latency_eq_0: if latency = 0 generate
    o <= i;
  end generate latency_eq_0;
  latency_gt_0: if latency >= 1 generate
    o <= reg_bank(latency-1);
    reg_bank_in(0) <= i;
    loop_gen: for idx in latency-2 downto 0 generate
      reg_bank_in(idx+1) <= reg_bank(idx);
    end generate loop_gen;
    sync_loop: for sync_idx in latency-1 downto 0 generate
      sync_proc: process (clk)
      begin
        if clk'event and clk = '1' then
          if ce = '1'  then
            reg_bank(sync_idx) <= reg_bank_in(sync_idx);
          end if;
        end if;
      end process sync_proc;
    end generate sync_loop;
  end generate latency_gt_0;
end behav;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
-- synopsys translate_off
library unisim;
use unisim.vcomponents.all;
-- synopsys translate_on
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity single_reg_w_init is
  generic (
    width: integer := 8;
    init_index: integer := 0;
    init_value: bit_vector := b"0000"
  );
  port (
    i: in std_logic_vector(width - 1 downto 0);
    ce: in std_logic;
    clr: in std_logic;
    clk: in std_logic;
    o: out std_logic_vector(width - 1 downto 0)
  );
end single_reg_w_init;
architecture structural of single_reg_w_init is
  function build_init_const(width: integer;
                            init_index: integer;
                            init_value: bit_vector)
    return std_logic_vector
  is
    variable result: std_logic_vector(width - 1 downto 0);
  begin
    if init_index = 0 then
      result := (others => '0');
    elsif init_index = 1 then
      result := (others => '0');
      result(0) := '1';
    else
      result := to_stdlogicvector(init_value);
    end if;
    return result;
  end;
  component fdre
    port (
      q: out std_ulogic;
      d: in  std_ulogic;
      c: in  std_ulogic;
      ce: in  std_ulogic;
      r: in  std_ulogic
    );
  end component;
  attribute syn_black_box of fdre: component is true;
  attribute fpga_dont_touch of fdre: component is "true";
  component fdse
    port (
      q: out std_ulogic;
      d: in  std_ulogic;
      c: in  std_ulogic;
      ce: in  std_ulogic;
      s: in  std_ulogic
    );
  end component;
  attribute syn_black_box of fdse: component is true;
  attribute fpga_dont_touch of fdse: component is "true";
  constant init_const: std_logic_vector(width - 1 downto 0)
    := build_init_const(width, init_index, init_value);
begin
  fd_prim_array: for index in 0 to width - 1 generate
    bit_is_0: if (init_const(index) = '0') generate
      fdre_comp: fdre
        port map (
          c => clk,
          d => i(index),
          q => o(index),
          ce => ce,
          r => clr
        );
    end generate;
    bit_is_1: if (init_const(index) = '1') generate
      fdse_comp: fdse
        port map (
          c => clk,
          d => i(index),
          q => o(index),
          ce => ce,
          s => clr
        );
    end generate;
  end generate;
end architecture structural;
-- synopsys translate_off
library unisim;
use unisim.vcomponents.all;
-- synopsys translate_on
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity synth_reg_w_init is
  generic (
    width: integer := 8;
    init_index: integer := 0;
    init_value: bit_vector := b"0000";
    latency: integer := 1
  );
  port (
    i: in std_logic_vector(width - 1 downto 0);
    ce: in std_logic;
    clr: in std_logic;
    clk: in std_logic;
    o: out std_logic_vector(width - 1 downto 0)
  );
end synth_reg_w_init;
architecture structural of synth_reg_w_init is
  component single_reg_w_init
    generic (
      width: integer := 8;
      init_index: integer := 0;
      init_value: bit_vector := b"0000"
    );
    port (
      i: in std_logic_vector(width - 1 downto 0);
      ce: in std_logic;
      clr: in std_logic;
      clk: in std_logic;
      o: out std_logic_vector(width - 1 downto 0)
    );
  end component;
  signal dly_i: std_logic_vector((latency + 1) * width - 1 downto 0);
  signal dly_clr: std_logic;
begin
  latency_eq_0: if (latency = 0) generate
    o <= i;
  end generate;
  latency_gt_0: if (latency >= 1) generate
    dly_i((latency + 1) * width - 1 downto latency * width) <= i
      after 200 ps;
    dly_clr <= clr after 200 ps;
    fd_array: for index in latency downto 1 generate
       reg_comp: single_reg_w_init
          generic map (
            width => width,
            init_index => init_index,
            init_value => init_value
          )
          port map (
            clk => clk,
            i => dly_i((index + 1) * width - 1 downto index * width),
            o => dly_i(index * width - 1 downto (index - 1) * width),
            ce => ce,
            clr => dly_clr
          );
    end generate;
    o <= dly_i(width - 1 downto 0);
  end generate;
end structural;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity concat1_91f6e5894e is
  port (
    in0 : in std_logic_vector((8 - 1) downto 0);
    in1 : in std_logic_vector((8 - 1) downto 0);
    in2 : in std_logic_vector((8 - 1) downto 0);
    in3 : in std_logic_vector((8 - 1) downto 0);
    y : out std_logic_vector((32 - 1) downto 0);
    clk : in std_logic;
    ce : in std_logic;
    clr : in std_logic);
end concat1_91f6e5894e;
architecture behavior of concat1_91f6e5894e is
  signal in0_1_23: unsigned((8 - 1) downto 0);
  signal in1_1_27: unsigned((8 - 1) downto 0);
  signal in2_1_31: unsigned((8 - 1) downto 0);
  signal in3_1_35: unsigned((8 - 1) downto 0);
  signal y_2_1_concat: unsigned((32 - 1) downto 0);
begin
  in0_1_23 <= std_logic_vector_to_unsigned(in0);
  in1_1_27 <= std_logic_vector_to_unsigned(in1);
  in2_1_31 <= std_logic_vector_to_unsigned(in2);
  in3_1_35 <= std_logic_vector_to_unsigned(in3);
  y_2_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(in0_1_23) & unsigned_to_std_logic_vector(in1_1_27) & unsigned_to_std_logic_vector(in2_1_31) & unsigned_to_std_logic_vector(in3_1_35));
  y <= unsigned_to_std_logic_vector(y_2_1_concat);
end behavior;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity reinterpret1_421868fdcf is
  port (
    input_port : in std_logic_vector((8 - 1) downto 0);
    output_port : out std_logic_vector((8 - 1) downto 0);
    clk : in std_logic;
    ce : in std_logic;
    clr : in std_logic);
end reinterpret1_421868fdcf;
architecture behavior of reinterpret1_421868fdcf is
  signal input_port_1_40: signed((8 - 1) downto 0);
  signal output_port_5_5_force: unsigned((8 - 1) downto 0);
begin
  input_port_1_40 <= std_logic_vector_to_signed(input_port);
  output_port_5_5_force <= signed_to_unsigned(input_port_1_40);
  output_port <= unsigned_to_std_logic_vector(output_port_5_5_force);
end behavior;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity reinterpret2_af838af55d is
  port (
    input_port : in std_logic_vector((8 - 1) downto 0);
    output_port : out std_logic_vector((8 - 1) downto 0);
    clk : in std_logic;
    ce : in std_logic;
    clr : in std_logic);
end reinterpret2_af838af55d;
architecture behavior of reinterpret2_af838af55d is
  signal input_port_1_40: signed((8 - 1) downto 0);
  signal output_port_5_5_force: unsigned((8 - 1) downto 0);
begin
  input_port_1_40 <= std_logic_vector_to_signed(input_port);
  output_port_5_5_force <= signed_to_unsigned(input_port_1_40);
  output_port <= unsigned_to_std_logic_vector(output_port_5_5_force);
end behavior;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity reinterpret3_8118b8df3f is
  port (
    input_port : in std_logic_vector((8 - 1) downto 0);
    output_port : out std_logic_vector((8 - 1) downto 0);
    clk : in std_logic;
    ce : in std_logic;
    clr : in std_logic);
end reinterpret3_8118b8df3f;
architecture behavior of reinterpret3_8118b8df3f is
  signal input_port_1_40: signed((8 - 1) downto 0);
  signal output_port_5_5_force: unsigned((8 - 1) downto 0);
begin
  input_port_1_40 <= std_logic_vector_to_signed(input_port);
  output_port_5_5_force <= signed_to_unsigned(input_port_1_40);
  output_port <= unsigned_to_std_logic_vector(output_port_5_5_force);
end behavior;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity reinterpret4_b77a7b0ce0 is
  port (
    input_port : in std_logic_vector((8 - 1) downto 0);
    output_port : out std_logic_vector((8 - 1) downto 0);
    clk : in std_logic;
    ce : in std_logic;
    clr : in std_logic);
end reinterpret4_b77a7b0ce0;
architecture behavior of reinterpret4_b77a7b0ce0 is
  signal input_port_1_40: signed((8 - 1) downto 0);
  signal output_port_5_5_force: unsigned((8 - 1) downto 0);
begin
  input_port_1_40 <= std_logic_vector_to_signed(input_port);
  output_port_5_5_force <= signed_to_unsigned(input_port_1_40);
  output_port <= unsigned_to_std_logic_vector(output_port_5_5_force);
end behavior;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity concat1_8254fe26d1 is
  port (
    in0 : in std_logic_vector((8 - 1) downto 0);
    in1 : in std_logic_vector((8 - 1) downto 0);
    in2 : in std_logic_vector((8 - 1) downto 0);
    in3 : in std_logic_vector((8 - 1) downto 0);
    y : out std_logic_vector((32 - 1) downto 0);
    clk : in std_logic;
    ce : in std_logic;
    clr : in std_logic);
end concat1_8254fe26d1;
architecture behavior of concat1_8254fe26d1 is
  signal in0_1_23: unsigned((8 - 1) downto 0);
  signal in1_1_27: unsigned((8 - 1) downto 0);
  signal in2_1_31: unsigned((8 - 1) downto 0);
  signal in3_1_35: unsigned((8 - 1) downto 0);
  signal y_2_1_concat: unsigned((32 - 1) downto 0);
begin
  in0_1_23 <= std_logic_vector_to_unsigned(in0);
  in1_1_27 <= std_logic_vector_to_unsigned(in1);
  in2_1_31 <= std_logic_vector_to_unsigned(in2);
  in3_1_35 <= std_logic_vector_to_unsigned(in3);
  y_2_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(in0_1_23) & unsigned_to_std_logic_vector(in1_1_27) & unsigned_to_std_logic_vector(in2_1_31) & unsigned_to_std_logic_vector(in3_1_35));
  y <= unsigned_to_std_logic_vector(y_2_1_concat);
end behavior;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity reinterpret1_209a7f1ccf is
  port (
    input_port : in std_logic_vector((8 - 1) downto 0);
    output_port : out std_logic_vector((8 - 1) downto 0);
    clk : in std_logic;
    ce : in std_logic;
    clr : in std_logic);
end reinterpret1_209a7f1ccf;
architecture behavior of reinterpret1_209a7f1ccf is
  signal input_port_1_40: signed((8 - 1) downto 0);
  signal output_port_5_5_force: unsigned((8 - 1) downto 0);
begin
  input_port_1_40 <= std_logic_vector_to_signed(input_port);
  output_port_5_5_force <= signed_to_unsigned(input_port_1_40);
  output_port <= unsigned_to_std_logic_vector(output_port_5_5_force);
end behavior;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity reinterpret2_f735414ec3 is
  port (
    input_port : in std_logic_vector((8 - 1) downto 0);
    output_port : out std_logic_vector((8 - 1) downto 0);
    clk : in std_logic;
    ce : in std_logic;
    clr : in std_logic);
end reinterpret2_f735414ec3;
architecture behavior of reinterpret2_f735414ec3 is
  signal input_port_1_40: signed((8 - 1) downto 0);
  signal output_port_5_5_force: unsigned((8 - 1) downto 0);
begin
  input_port_1_40 <= std_logic_vector_to_signed(input_port);
  output_port_5_5_force <= signed_to_unsigned(input_port_1_40);
  output_port <= unsigned_to_std_logic_vector(output_port_5_5_force);
end behavior;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity reinterpret3_f487f886c1 is
  port (
    input_port : in std_logic_vector((8 - 1) downto 0);
    output_port : out std_logic_vector((8 - 1) downto 0);
    clk : in std_logic;
    ce : in std_logic;
    clr : in std_logic);
end reinterpret3_f487f886c1;
architecture behavior of reinterpret3_f487f886c1 is
  signal input_port_1_40: signed((8 - 1) downto 0);
  signal output_port_5_5_force: unsigned((8 - 1) downto 0);
begin
  input_port_1_40 <= std_logic_vector_to_signed(input_port);
  output_port_5_5_force <= signed_to_unsigned(input_port_1_40);
  output_port <= unsigned_to_std_logic_vector(output_port_5_5_force);
end behavior;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity reinterpret4_5b4e0dc295 is
  port (
    input_port : in std_logic_vector((8 - 1) downto 0);
    output_port : out std_logic_vector((8 - 1) downto 0);
    clk : in std_logic;
    ce : in std_logic;
    clr : in std_logic);
end reinterpret4_5b4e0dc295;
architecture behavior of reinterpret4_5b4e0dc295 is
  signal input_port_1_40: signed((8 - 1) downto 0);
  signal output_port_5_5_force: unsigned((8 - 1) downto 0);
begin
  input_port_1_40 <= std_logic_vector_to_signed(input_port);
  output_port_5_5_force <= signed_to_unsigned(input_port_1_40);
  output_port <= unsigned_to_std_logic_vector(output_port_5_5_force);
end behavior;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity reinterpret4_2cede6fcef is
  port (
    input_port : in std_logic_vector((8 - 1) downto 0);
    output_port : out std_logic_vector((8 - 1) downto 0);
    clk : in std_logic;
    ce : in std_logic;
    clr : in std_logic);
end reinterpret4_2cede6fcef;
architecture behavior of reinterpret4_2cede6fcef is
  signal input_port_1_40: unsigned((8 - 1) downto 0);
  signal output_port_5_5_force: signed((8 - 1) downto 0);
begin
  input_port_1_40 <= std_logic_vector_to_unsigned(input_port);
  output_port_5_5_force <= unsigned_to_signed(input_port_1_40);
  output_port <= signed_to_std_logic_vector(output_port_5_5_force);
end behavior;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity reinterpret5_ddc5355546 is
  port (
    input_port : in std_logic_vector((8 - 1) downto 0);
    output_port : out std_logic_vector((8 - 1) downto 0);
    clk : in std_logic;
    ce : in std_logic;
    clr : in std_logic);
end reinterpret5_ddc5355546;
architecture behavior of reinterpret5_ddc5355546 is
  signal input_port_1_40: unsigned((8 - 1) downto 0);
  signal output_port_5_5_force: signed((8 - 1) downto 0);
begin
  input_port_1_40 <= std_logic_vector_to_unsigned(input_port);
  output_port_5_5_force <= unsigned_to_signed(input_port_1_40);
  output_port <= signed_to_std_logic_vector(output_port_5_5_force);
end behavior;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity reinterpret6_0562bbbdfa is
  port (
    input_port : in std_logic_vector((8 - 1) downto 0);
    output_port : out std_logic_vector((8 - 1) downto 0);
    clk : in std_logic;
    ce : in std_logic;
    clr : in std_logic);
end reinterpret6_0562bbbdfa;
architecture behavior of reinterpret6_0562bbbdfa is
  signal input_port_1_40: unsigned((8 - 1) downto 0);
  signal output_port_5_5_force: signed((8 - 1) downto 0);
begin
  input_port_1_40 <= std_logic_vector_to_unsigned(input_port);
  output_port_5_5_force <= unsigned_to_signed(input_port_1_40);
  output_port <= signed_to_std_logic_vector(output_port_5_5_force);
end behavior;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity reinterpret7_28693a4e8c is
  port (
    input_port : in std_logic_vector((8 - 1) downto 0);
    output_port : out std_logic_vector((8 - 1) downto 0);
    clk : in std_logic;
    ce : in std_logic;
    clr : in std_logic);
end reinterpret7_28693a4e8c;
architecture behavior of reinterpret7_28693a4e8c is
  signal input_port_1_40: unsigned((8 - 1) downto 0);
  signal output_port_5_5_force: signed((8 - 1) downto 0);
begin
  input_port_1_40 <= std_logic_vector_to_unsigned(input_port);
  output_port_5_5_force <= unsigned_to_signed(input_port_1_40);
  output_port <= signed_to_std_logic_vector(output_port_5_5_force);
end behavior;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity bit0_eab550d1c0 is
  port (
    x : in std_logic_vector((32 - 1) downto 0);
    y : out std_logic_vector((8 - 1) downto 0);
    clk : in std_logic;
    ce : in std_logic;
    clr : in std_logic);
end bit0_eab550d1c0;
architecture behavior of bit0_eab550d1c0 is
  signal x_1_22: unsigned((32 - 1) downto 0);
  signal y_2_1_slice: unsigned((8 - 1) downto 0);
begin
  x_1_22 <= std_logic_vector_to_unsigned(x);
  y_2_1_slice <= u2u_slice(x_1_22, 7, 0);
  y <= unsigned_to_std_logic_vector(y_2_1_slice);
end behavior;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity bit16_f5ebc38801 is
  port (
    x : in std_logic_vector((32 - 1) downto 0);
    y : out std_logic_vector((8 - 1) downto 0);
    clk : in std_logic;
    ce : in std_logic;
    clr : in std_logic);
end bit16_f5ebc38801;
architecture behavior of bit16_f5ebc38801 is
  signal x_1_22: unsigned((32 - 1) downto 0);
  signal y_2_1_slice: unsigned((8 - 1) downto 0);
begin
  x_1_22 <= std_logic_vector_to_unsigned(x);
  y_2_1_slice <= u2u_slice(x_1_22, 23, 16);
  y <= unsigned_to_std_logic_vector(y_2_1_slice);
end behavior;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity bit24_c653e87f15 is
  port (
    x : in std_logic_vector((32 - 1) downto 0);
    y : out std_logic_vector((8 - 1) downto 0);
    clk : in std_logic;
    ce : in std_logic;
    clr : in std_logic);
end bit24_c653e87f15;
architecture behavior of bit24_c653e87f15 is
  signal x_1_22: unsigned((32 - 1) downto 0);
  signal y_2_1_slice: unsigned((8 - 1) downto 0);
begin
  x_1_22 <= std_logic_vector_to_unsigned(x);
  y_2_1_slice <= u2u_slice(x_1_22, 31, 24);
  y <= unsigned_to_std_logic_vector(y_2_1_slice);
end behavior;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity bit8_6a4da2d14b is
  port (
    x : in std_logic_vector((32 - 1) downto 0);
    y : out std_logic_vector((8 - 1) downto 0);
    clk : in std_logic;
    ce : in std_logic;
    clr : in std_logic);
end bit8_6a4da2d14b;
architecture behavior of bit8_6a4da2d14b is
  signal x_1_22: unsigned((32 - 1) downto 0);
  signal y_2_1_slice: unsigned((8 - 1) downto 0);
begin
  x_1_22 <= std_logic_vector_to_unsigned(x);
  y_2_1_slice <= u2u_slice(x_1_22, 15, 8);
  y <= unsigned_to_std_logic_vector(y_2_1_slice);
end behavior;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity reinterpret4_0bfe5a8dd8 is
  port (
    input_port : in std_logic_vector((8 - 1) downto 0);
    output_port : out std_logic_vector((8 - 1) downto 0);
    clk : in std_logic;
    ce : in std_logic;
    clr : in std_logic);
end reinterpret4_0bfe5a8dd8;
architecture behavior of reinterpret4_0bfe5a8dd8 is
  signal input_port_1_40: unsigned((8 - 1) downto 0);
  signal output_port_5_5_force: signed((8 - 1) downto 0);
begin
  input_port_1_40 <= std_logic_vector_to_unsigned(input_port);
  output_port_5_5_force <= unsigned_to_signed(input_port_1_40);
  output_port <= signed_to_std_logic_vector(output_port_5_5_force);
end behavior;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity reinterpret5_ad5fcc0cc6 is
  port (
    input_port : in std_logic_vector((8 - 1) downto 0);
    output_port : out std_logic_vector((8 - 1) downto 0);
    clk : in std_logic;
    ce : in std_logic;
    clr : in std_logic);
end reinterpret5_ad5fcc0cc6;
architecture behavior of reinterpret5_ad5fcc0cc6 is
  signal input_port_1_40: unsigned((8 - 1) downto 0);
  signal output_port_5_5_force: signed((8 - 1) downto 0);
begin
  input_port_1_40 <= std_logic_vector_to_unsigned(input_port);
  output_port_5_5_force <= unsigned_to_signed(input_port_1_40);
  output_port <= signed_to_std_logic_vector(output_port_5_5_force);
end behavior;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity reinterpret6_0f88bc95f6 is
  port (
    input_port : in std_logic_vector((8 - 1) downto 0);
    output_port : out std_logic_vector((8 - 1) downto 0);
    clk : in std_logic;
    ce : in std_logic;
    clr : in std_logic);
end reinterpret6_0f88bc95f6;
architecture behavior of reinterpret6_0f88bc95f6 is
  signal input_port_1_40: unsigned((8 - 1) downto 0);
  signal output_port_5_5_force: signed((8 - 1) downto 0);
begin
  input_port_1_40 <= std_logic_vector_to_unsigned(input_port);
  output_port_5_5_force <= unsigned_to_signed(input_port_1_40);
  output_port <= signed_to_std_logic_vector(output_port_5_5_force);
end behavior;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity reinterpret7_1f25723006 is
  port (
    input_port : in std_logic_vector((8 - 1) downto 0);
    output_port : out std_logic_vector((8 - 1) downto 0);
    clk : in std_logic;
    ce : in std_logic;
    clr : in std_logic);
end reinterpret7_1f25723006;
architecture behavior of reinterpret7_1f25723006 is
  signal input_port_1_40: unsigned((8 - 1) downto 0);
  signal output_port_5_5_force: signed((8 - 1) downto 0);
begin
  input_port_1_40 <= std_logic_vector_to_unsigned(input_port);
  output_port_5_5_force <= unsigned_to_signed(input_port_1_40);
  output_port <= signed_to_std_logic_vector(output_port_5_5_force);
end behavior;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity bit0_5b70faa9e1 is
  port (
    x : in std_logic_vector((32 - 1) downto 0);
    y : out std_logic_vector((8 - 1) downto 0);
    clk : in std_logic;
    ce : in std_logic;
    clr : in std_logic);
end bit0_5b70faa9e1;
architecture behavior of bit0_5b70faa9e1 is
  signal x_1_22: unsigned((32 - 1) downto 0);
  signal y_2_1_slice: unsigned((8 - 1) downto 0);
begin
  x_1_22 <= std_logic_vector_to_unsigned(x);
  y_2_1_slice <= u2u_slice(x_1_22, 7, 0);
  y <= unsigned_to_std_logic_vector(y_2_1_slice);
end behavior;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity bit16_0899a8c2cd is
  port (
    x : in std_logic_vector((32 - 1) downto 0);
    y : out std_logic_vector((8 - 1) downto 0);
    clk : in std_logic;
    ce : in std_logic;
    clr : in std_logic);
end bit16_0899a8c2cd;
architecture behavior of bit16_0899a8c2cd is
  signal x_1_22: unsigned((32 - 1) downto 0);
  signal y_2_1_slice: unsigned((8 - 1) downto 0);
begin
  x_1_22 <= std_logic_vector_to_unsigned(x);
  y_2_1_slice <= u2u_slice(x_1_22, 23, 16);
  y <= unsigned_to_std_logic_vector(y_2_1_slice);
end behavior;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity bit24_6703f73bb4 is
  port (
    x : in std_logic_vector((32 - 1) downto 0);
    y : out std_logic_vector((8 - 1) downto 0);
    clk : in std_logic;
    ce : in std_logic;
    clr : in std_logic);
end bit24_6703f73bb4;
architecture behavior of bit24_6703f73bb4 is
  signal x_1_22: unsigned((32 - 1) downto 0);
  signal y_2_1_slice: unsigned((8 - 1) downto 0);
begin
  x_1_22 <= std_logic_vector_to_unsigned(x);
  y_2_1_slice <= u2u_slice(x_1_22, 31, 24);
  y <= unsigned_to_std_logic_vector(y_2_1_slice);
end behavior;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity bit8_a5f685fcb4 is
  port (
    x : in std_logic_vector((32 - 1) downto 0);
    y : out std_logic_vector((8 - 1) downto 0);
    clk : in std_logic;
    ce : in std_logic;
    clr : in std_logic);
end bit8_a5f685fcb4;
architecture behavior of bit8_a5f685fcb4 is
  signal x_1_22: unsigned((32 - 1) downto 0);
  signal y_2_1_slice: unsigned((8 - 1) downto 0);
begin
  x_1_22 <= std_logic_vector_to_unsigned(x);
  y_2_1_slice <= u2u_slice(x_1_22, 15, 8);
  y <= unsigned_to_std_logic_vector(y_2_1_slice);
end behavior;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity concat_d694665e71 is
  port (
    in0 : in std_logic_vector((16 - 1) downto 0);
    in1 : in std_logic_vector((16 - 1) downto 0);
    in2 : in std_logic_vector((1 - 1) downto 0);
    in3 : in std_logic_vector((1 - 1) downto 0);
    in4 : in std_logic_vector((1 - 1) downto 0);
    in5 : in std_logic_vector((16 - 1) downto 0);
    in6 : in std_logic_vector((16 - 1) downto 0);
    in7 : in std_logic_vector((1 - 1) downto 0);
    y : out std_logic_vector((68 - 1) downto 0);
    clk : in std_logic;
    ce : in std_logic;
    clr : in std_logic);
end concat_d694665e71;
architecture behavior of concat_d694665e71 is
  signal in0_1_23: unsigned((16 - 1) downto 0);
  signal in1_1_27: unsigned((16 - 1) downto 0);
  signal in2_1_31: boolean;
  signal in3_1_35: unsigned((1 - 1) downto 0);
  signal in4_1_39: boolean;
  signal in5_1_43: unsigned((16 - 1) downto 0);
  signal in6_1_47: unsigned((16 - 1) downto 0);
  signal in7_1_51: unsigned((1 - 1) downto 0);
  signal y_2_1_concat: unsigned((68 - 1) downto 0);
begin
  in0_1_23 <= std_logic_vector_to_unsigned(in0);
  in1_1_27 <= std_logic_vector_to_unsigned(in1);
  in2_1_31 <= ((in2) = "1");
  in3_1_35 <= std_logic_vector_to_unsigned(in3);
  in4_1_39 <= ((in4) = "1");
  in5_1_43 <= std_logic_vector_to_unsigned(in5);
  in6_1_47 <= std_logic_vector_to_unsigned(in6);
  in7_1_51 <= std_logic_vector_to_unsigned(in7);
  y_2_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(in0_1_23) & unsigned_to_std_logic_vector(in1_1_27) & boolean_to_vector(in2_1_31) & unsigned_to_std_logic_vector(in3_1_35) & boolean_to_vector(in4_1_39) & unsigned_to_std_logic_vector(in5_1_43) & unsigned_to_std_logic_vector(in6_1_47) & unsigned_to_std_logic_vector(in7_1_51));
  y <= unsigned_to_std_logic_vector(y_2_1_concat);
end behavior;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity concat1_3055210e70 is
  port (
    in0 : in std_logic_vector((16 - 1) downto 0);
    in1 : in std_logic_vector((76 - 1) downto 0);
    y : out std_logic_vector((92 - 1) downto 0);
    clk : in std_logic;
    ce : in std_logic;
    clr : in std_logic);
end concat1_3055210e70;
architecture behavior of concat1_3055210e70 is
  signal in0_1_23: unsigned((16 - 1) downto 0);
  signal in1_1_27: unsigned((76 - 1) downto 0);
  signal y_2_1_concat: unsigned((92 - 1) downto 0);
begin
  in0_1_23 <= std_logic_vector_to_unsigned(in0);
  in1_1_27 <= std_logic_vector_to_unsigned(in1);
  y_2_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(in0_1_23) & unsigned_to_std_logic_vector(in1_1_27));
  y <= unsigned_to_std_logic_vector(y_2_1_concat);
end behavior;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity concat2_7c7ec05f81 is
  port (
    in0 : in std_logic_vector((8 - 1) downto 0);
    in1 : in std_logic_vector((68 - 1) downto 0);
    y : out std_logic_vector((76 - 1) downto 0);
    clk : in std_logic;
    ce : in std_logic;
    clr : in std_logic);
end concat2_7c7ec05f81;
architecture behavior of concat2_7c7ec05f81 is
  signal in0_1_23: unsigned((8 - 1) downto 0);
  signal in1_1_27: unsigned((68 - 1) downto 0);
  signal y_2_1_concat: unsigned((76 - 1) downto 0);
begin
  in0_1_23 <= std_logic_vector_to_unsigned(in0);
  in1_1_27 <= std_logic_vector_to_unsigned(in1);
  y_2_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(in0_1_23) & unsigned_to_std_logic_vector(in1_1_27));
  y <= unsigned_to_std_logic_vector(y_2_1_concat);
end behavior;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity concat3_c4dc34b1a7 is
  port (
    in0 : in std_logic_vector((1 - 1) downto 0);
    in1 : in std_logic_vector((1 - 1) downto 0);
    in2 : in std_logic_vector((1 - 1) downto 0);
    in3 : in std_logic_vector((1 - 1) downto 0);
    in4 : in std_logic_vector((1 - 1) downto 0);
    in5 : in std_logic_vector((1 - 1) downto 0);
    in6 : in std_logic_vector((1 - 1) downto 0);
    in7 : in std_logic_vector((1 - 1) downto 0);
    y : out std_logic_vector((8 - 1) downto 0);
    clk : in std_logic;
    ce : in std_logic;
    clr : in std_logic);
end concat3_c4dc34b1a7;
architecture behavior of concat3_c4dc34b1a7 is
  signal in0_1_23: unsigned((1 - 1) downto 0);
  signal in1_1_27: unsigned((1 - 1) downto 0);
  signal in2_1_31: unsigned((1 - 1) downto 0);
  signal in3_1_35: unsigned((1 - 1) downto 0);
  signal in4_1_39: unsigned((1 - 1) downto 0);
  signal in5_1_43: unsigned((1 - 1) downto 0);
  signal in6_1_47: unsigned((1 - 1) downto 0);
  signal in7_1_51: unsigned((1 - 1) downto 0);
  signal y_2_1_concat: unsigned((8 - 1) downto 0);
begin
  in0_1_23 <= std_logic_vector_to_unsigned(in0);
  in1_1_27 <= std_logic_vector_to_unsigned(in1);
  in2_1_31 <= std_logic_vector_to_unsigned(in2);
  in3_1_35 <= std_logic_vector_to_unsigned(in3);
  in4_1_39 <= std_logic_vector_to_unsigned(in4);
  in5_1_43 <= std_logic_vector_to_unsigned(in5);
  in6_1_47 <= std_logic_vector_to_unsigned(in6);
  in7_1_51 <= std_logic_vector_to_unsigned(in7);
  y_2_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(in0_1_23) & unsigned_to_std_logic_vector(in1_1_27) & unsigned_to_std_logic_vector(in2_1_31) & unsigned_to_std_logic_vector(in3_1_35) & unsigned_to_std_logic_vector(in4_1_39) & unsigned_to_std_logic_vector(in5_1_43) & unsigned_to_std_logic_vector(in6_1_47) & unsigned_to_std_logic_vector(in7_1_51));
  y <= unsigned_to_std_logic_vector(y_2_1_concat);
end behavior;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity constant1_699d7f1eeb is
  port (
    op : out std_logic_vector((16 - 1) downto 0);
    clk : in std_logic;
    ce : in std_logic;
    clr : in std_logic);
end constant1_699d7f1eeb;
architecture behavior of constant1_699d7f1eeb is
begin
  op <= "0000000000000000";
end behavior;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity constant2_5f1cd7b048 is
  port (
    op : out std_logic_vector((1 - 1) downto 0);
    clk : in std_logic;
    ce : in std_logic;
    clr : in std_logic);
end constant2_5f1cd7b048;
architecture behavior of constant2_5f1cd7b048 is
begin
  op <= "0";
end behavior;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity constant3_d786e11d4e is
  port (
    op : out std_logic_vector((16 - 1) downto 0);
    clk : in std_logic;
    ce : in std_logic;
    clr : in std_logic);
end constant3_d786e11d4e;
architecture behavior of constant3_d786e11d4e is
begin
  op <= "0000000000000000";
end behavior;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity constant4_21438855e4 is
  port (
    op : out std_logic_vector((16 - 1) downto 0);
    clk : in std_logic;
    ce : in std_logic;
    clr : in std_logic);
end constant4_21438855e4;
architecture behavior of constant4_21438855e4 is
begin
  op <= "0000000000000000";
end behavior;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity constant5_075adb46bf is
  port (
    op : out std_logic_vector((16 - 1) downto 0);
    clk : in std_logic;
    ce : in std_logic;
    clr : in std_logic);
end constant5_075adb46bf;
architecture behavior of constant5_075adb46bf is
begin
  op <= "0000000000000000";
end behavior;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity constant6_49c14364ee is
  port (
    op : out std_logic_vector((16 - 1) downto 0);
    clk : in std_logic;
    ce : in std_logic;
    clr : in std_logic);
end constant6_49c14364ee;
architecture behavior of constant6_49c14364ee is
begin
  op <= "0000000000000000";
end behavior;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity concat_df7186a2e1 is
  port (
    in0 : in std_logic_vector((8 - 1) downto 0);
    in1 : in std_logic_vector((8 - 1) downto 0);
    y : out std_logic_vector((16 - 1) downto 0);
    clk : in std_logic;
    ce : in std_logic;
    clr : in std_logic);
end concat_df7186a2e1;
architecture behavior of concat_df7186a2e1 is
  signal in0_1_23: unsigned((8 - 1) downto 0);
  signal in1_1_27: unsigned((8 - 1) downto 0);
  signal y_2_1_concat: unsigned((16 - 1) downto 0);
begin
  in0_1_23 <= std_logic_vector_to_unsigned(in0);
  in1_1_27 <= std_logic_vector_to_unsigned(in1);
  y_2_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(in0_1_23) & unsigned_to_std_logic_vector(in1_1_27));
  y <= unsigned_to_std_logic_vector(y_2_1_concat);
end behavior;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity constant8_cb133a1117 is
  port (
    op : out std_logic_vector((8 - 1) downto 0);
    clk : in std_logic;
    ce : in std_logic;
    clr : in std_logic);
end constant8_cb133a1117;
architecture behavior of constant8_cb133a1117 is
begin
  op <= "00000000";
end behavior;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity xlpassthrough is
    generic (
        din_width    : integer := 16;
        dout_width   : integer := 16
        );
    port (
        din : in std_logic_vector (din_width-1 downto 0);
        dout : out std_logic_vector (dout_width-1 downto 0));
end xlpassthrough;
architecture passthrough_arch of xlpassthrough is
begin
  dout <= din;
end passthrough_arch;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity lsb1_e6a95c1af1 is
  port (
    x : in std_logic_vector((8 - 1) downto 0);
    y : out std_logic_vector((1 - 1) downto 0);
    clk : in std_logic;
    ce : in std_logic;
    clr : in std_logic);
end lsb1_e6a95c1af1;
architecture behavior of lsb1_e6a95c1af1 is
  signal x_1_22: unsigned((8 - 1) downto 0);
  signal slice_2_34: unsigned((1 - 1) downto 0);
  signal y_2_1_convert: boolean;
begin
  x_1_22 <= std_logic_vector_to_unsigned(x);
  slice_2_34 <= u2u_slice(x_1_22, 0, 0);
  y_2_1_convert <= (slice_2_34 /= "0");
  y <= boolean_to_vector(y_2_1_convert);
end behavior;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity lsb3_b3a1c0e2cd is
  port (
    x : in std_logic_vector((8 - 1) downto 0);
    y : out std_logic_vector((1 - 1) downto 0);
    clk : in std_logic;
    ce : in std_logic;
    clr : in std_logic);
end lsb3_b3a1c0e2cd;
architecture behavior of lsb3_b3a1c0e2cd is
  signal x_1_22: unsigned((8 - 1) downto 0);
  signal slice_2_34: unsigned((1 - 1) downto 0);
  signal y_2_1_convert: boolean;
begin
  x_1_22 <= std_logic_vector_to_unsigned(x);
  slice_2_34 <= u2u_slice(x_1_22, 2, 2);
  y_2_1_convert <= (slice_2_34 /= "0");
  y <= boolean_to_vector(y_2_1_convert);
end behavior;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity sl_5lsb_82c15f848e is
  port (
    x : in std_logic_vector((8 - 1) downto 0);
    y : out std_logic_vector((5 - 1) downto 0);
    clk : in std_logic;
    ce : in std_logic;
    clr : in std_logic);
end sl_5lsb_82c15f848e;
architecture behavior of sl_5lsb_82c15f848e is
  signal x_1_22: unsigned((8 - 1) downto 0);
  signal y_2_1_slice: unsigned((5 - 1) downto 0);
begin
  x_1_22 <= std_logic_vector_to_unsigned(x);
  y_2_1_slice <= u2u_slice(x_1_22, 4, 0);
  y <= unsigned_to_std_logic_vector(y_2_1_slice);
end behavior;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity sl_5lsb_1_85931bdd03 is
  port (
    x : in std_logic_vector((8 - 1) downto 0);
    y : out std_logic_vector((5 - 1) downto 0);
    clk : in std_logic;
    ce : in std_logic;
    clr : in std_logic);
end sl_5lsb_1_85931bdd03;
architecture behavior of sl_5lsb_1_85931bdd03 is
  signal x_1_22: unsigned((8 - 1) downto 0);
  signal y_2_1_slice: unsigned((5 - 1) downto 0);
begin
  x_1_22 <= std_logic_vector_to_unsigned(x);
  y_2_1_slice <= u2u_slice(x_1_22, 4, 0);
  y <= unsigned_to_std_logic_vector(y_2_1_slice);
end behavior;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity sl_byte0_4d9050d309 is
  port (
    x : in std_logic_vector((32 - 1) downto 0);
    y : out std_logic_vector((8 - 1) downto 0);
    clk : in std_logic;
    ce : in std_logic;
    clr : in std_logic);
end sl_byte0_4d9050d309;
architecture behavior of sl_byte0_4d9050d309 is
  signal x_1_22: unsigned((32 - 1) downto 0);
  signal y_2_1_slice: unsigned((8 - 1) downto 0);
begin
  x_1_22 <= std_logic_vector_to_unsigned(x);
  y_2_1_slice <= u2u_slice(x_1_22, 7, 0);
  y <= unsigned_to_std_logic_vector(y_2_1_slice);
end behavior;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity sl_byte1_21a54b9e61 is
  port (
    x : in std_logic_vector((32 - 1) downto 0);
    y : out std_logic_vector((8 - 1) downto 0);
    clk : in std_logic;
    ce : in std_logic;
    clr : in std_logic);
end sl_byte1_21a54b9e61;
architecture behavior of sl_byte1_21a54b9e61 is
  signal x_1_22: unsigned((32 - 1) downto 0);
  signal y_2_1_slice: unsigned((8 - 1) downto 0);
begin
  x_1_22 <= std_logic_vector_to_unsigned(x);
  y_2_1_slice <= u2u_slice(x_1_22, 15, 8);
  y <= unsigned_to_std_logic_vector(y_2_1_slice);
end behavior;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity sl_byte2_3628a88f76 is
  port (
    x : in std_logic_vector((32 - 1) downto 0);
    y : out std_logic_vector((8 - 1) downto 0);
    clk : in std_logic;
    ce : in std_logic;
    clr : in std_logic);
end sl_byte2_3628a88f76;
architecture behavior of sl_byte2_3628a88f76 is
  signal x_1_22: unsigned((32 - 1) downto 0);
  signal y_2_1_slice: unsigned((8 - 1) downto 0);
begin
  x_1_22 <= std_logic_vector_to_unsigned(x);
  y_2_1_slice <= u2u_slice(x_1_22, 23, 16);
  y <= unsigned_to_std_logic_vector(y_2_1_slice);
end behavior;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity sl_byte3_9d1210cfbd is
  port (
    x : in std_logic_vector((32 - 1) downto 0);
    y : out std_logic_vector((8 - 1) downto 0);
    clk : in std_logic;
    ce : in std_logic;
    clr : in std_logic);
end sl_byte3_9d1210cfbd;
architecture behavior of sl_byte3_9d1210cfbd is
  signal x_1_22: unsigned((32 - 1) downto 0);
  signal y_2_1_slice: unsigned((8 - 1) downto 0);
begin
  x_1_22 <= std_logic_vector_to_unsigned(x);
  y_2_1_slice <= u2u_slice(x_1_22, 31, 24);
  y <= unsigned_to_std_logic_vector(y_2_1_slice);
end behavior;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity inverter2_2ab0852d89 is
  port (
    ip : in std_logic_vector((1 - 1) downto 0);
    op : out std_logic_vector((1 - 1) downto 0);
    clk : in std_logic;
    ce : in std_logic;
    clr : in std_logic);
end inverter2_2ab0852d89;
architecture behavior of inverter2_2ab0852d89 is
  signal ip_1_26: boolean;
  type array_type_op_mem_22_20 is array (0 to (1 - 1)) of boolean;
  signal op_mem_22_20: array_type_op_mem_22_20 := (
    0 => false);
  signal op_mem_22_20_front_din: boolean;
  signal op_mem_22_20_back: boolean;
  signal op_mem_22_20_push_front_pop_back_en: std_logic;
  signal internal_ip_12_1_bitnot: boolean;
begin
  ip_1_26 <= ((ip) = "1");
  op_mem_22_20_back <= op_mem_22_20(0);
  proc_op_mem_22_20: process (clk)
  is
    variable i: integer;
  begin
    if (clk'event and (clk = '1')) then
      if ((ce = '1') and (op_mem_22_20_push_front_pop_back_en = '1')) then
        op_mem_22_20(0) <= op_mem_22_20_front_din;
      end if;
    end if;
  end process proc_op_mem_22_20;
  internal_ip_12_1_bitnot <= ((not boolean_to_vector(ip_1_26)) = "1");
  op_mem_22_20_front_din <= internal_ip_12_1_bitnot;
  op_mem_22_20_push_front_pop_back_en <= '1';
  op <= boolean_to_vector(op_mem_22_20_back);
end behavior;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity logical1_dc01bcb7e5 is
  port (
    d0 : in std_logic_vector((1 - 1) downto 0);
    d1 : in std_logic_vector((1 - 1) downto 0);
    y : out std_logic_vector((1 - 1) downto 0);
    clk : in std_logic;
    ce : in std_logic;
    clr : in std_logic);
end logical1_dc01bcb7e5;
architecture behavior of logical1_dc01bcb7e5 is
  signal d0_1_24: boolean;
  signal d1_1_27: boolean;
  signal fully_2_1_bit: boolean;
begin
  d0_1_24 <= ((d0) = "1");
  d1_1_27 <= ((d1) = "1");
  fully_2_1_bit <= ((boolean_to_vector(d0_1_24) and boolean_to_vector(d1_1_27)) = "1");
  y <= boolean_to_vector(fully_2_1_bit);
end behavior;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity concat_bc5e36d4ea is
  port (
    in0 : in std_logic_vector((1 - 1) downto 0);
    in1 : in std_logic_vector((7 - 1) downto 0);
    y : out std_logic_vector((8 - 1) downto 0);
    clk : in std_logic;
    ce : in std_logic;
    clr : in std_logic);
end concat_bc5e36d4ea;
architecture behavior of concat_bc5e36d4ea is
  signal in0_1_23: unsigned((1 - 1) downto 0);
  signal in1_1_27: unsigned((7 - 1) downto 0);
  signal y_2_1_concat: unsigned((8 - 1) downto 0);
begin
  in0_1_23 <= std_logic_vector_to_unsigned(in0);
  in1_1_27 <= std_logic_vector_to_unsigned(in1);
  y_2_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(in0_1_23) & unsigned_to_std_logic_vector(in1_1_27));
  y <= unsigned_to_std_logic_vector(y_2_1_concat);
end behavior;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity inverter_e88d30344f is
  port (
    ip : in std_logic_vector((1 - 1) downto 0);
    op : out std_logic_vector((1 - 1) downto 0);
    clk : in std_logic;
    ce : in std_logic;
    clr : in std_logic);
end inverter_e88d30344f;
architecture behavior of inverter_e88d30344f is
  signal ip_1_26: unsigned((1 - 1) downto 0);
  type array_type_op_mem_22_20 is array (0 to (1 - 1)) of unsigned((1 - 1) downto 0);
  signal op_mem_22_20: array_type_op_mem_22_20 := (
    0 => "0");
  signal op_mem_22_20_front_din: unsigned((1 - 1) downto 0);
  signal op_mem_22_20_back: unsigned((1 - 1) downto 0);
  signal op_mem_22_20_push_front_pop_back_en: std_logic;
  signal internal_ip_12_1_bitnot: unsigned((1 - 1) downto 0);
begin
  ip_1_26 <= std_logic_vector_to_unsigned(ip);
  op_mem_22_20_back <= op_mem_22_20(0);
  proc_op_mem_22_20: process (clk)
  is
    variable i: integer;
  begin
    if (clk'event and (clk = '1')) then
      if ((ce = '1') and (op_mem_22_20_push_front_pop_back_en = '1')) then
        op_mem_22_20(0) <= op_mem_22_20_front_din;
      end if;
    end if;
  end process proc_op_mem_22_20;
  internal_ip_12_1_bitnot <= std_logic_vector_to_unsigned(not unsigned_to_std_logic_vector(ip_1_26));
  op_mem_22_20_push_front_pop_back_en <= '0';
  op <= unsigned_to_std_logic_vector(internal_ip_12_1_bitnot);
end behavior;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity reinterpret_bb5704daa0 is
  port (
    input_port : in std_logic_vector((8 - 1) downto 0);
    output_port : out std_logic_vector((8 - 1) downto 0);
    clk : in std_logic;
    ce : in std_logic;
    clr : in std_logic);
end reinterpret_bb5704daa0;
architecture behavior of reinterpret_bb5704daa0 is
  signal input_port_1_40: unsigned((8 - 1) downto 0);
  signal output_port_5_5_force: signed((8 - 1) downto 0);
begin
  input_port_1_40 <= std_logic_vector_to_unsigned(input_port);
  output_port_5_5_force <= unsigned_to_signed(input_port_1_40);
  output_port <= signed_to_std_logic_vector(output_port_5_5_force);
end behavior;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity slice_ada6dabeed is
  port (
    x : in std_logic_vector((8 - 1) downto 0);
    y : out std_logic_vector((1 - 1) downto 0);
    clk : in std_logic;
    ce : in std_logic;
    clr : in std_logic);
end slice_ada6dabeed;
architecture behavior of slice_ada6dabeed is
  signal x_1_22: unsigned((8 - 1) downto 0);
  signal y_2_1_slice: unsigned((1 - 1) downto 0);
begin
  x_1_22 <= std_logic_vector_to_unsigned(x);
  y_2_1_slice <= u2u_slice(x_1_22, 7, 7);
  y <= unsigned_to_std_logic_vector(y_2_1_slice);
end behavior;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity slice1_024135aade is
  port (
    x : in std_logic_vector((8 - 1) downto 0);
    y : out std_logic_vector((7 - 1) downto 0);
    clk : in std_logic;
    ce : in std_logic;
    clr : in std_logic);
end slice1_024135aade;
architecture behavior of slice1_024135aade is
  signal x_1_22: unsigned((8 - 1) downto 0);
  signal y_2_1_slice: unsigned((7 - 1) downto 0);
begin
  x_1_22 <= std_logic_vector_to_unsigned(x);
  y_2_1_slice <= u2u_slice(x_1_22, 6, 0);
  y <= unsigned_to_std_logic_vector(y_2_1_slice);
end behavior;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity concat_ddc54e5835 is
  port (
    in0 : in std_logic_vector((1 - 1) downto 0);
    in1 : in std_logic_vector((7 - 1) downto 0);
    y : out std_logic_vector((8 - 1) downto 0);
    clk : in std_logic;
    ce : in std_logic;
    clr : in std_logic);
end concat_ddc54e5835;
architecture behavior of concat_ddc54e5835 is
  signal in0_1_23: unsigned((1 - 1) downto 0);
  signal in1_1_27: unsigned((7 - 1) downto 0);
  signal y_2_1_concat: unsigned((8 - 1) downto 0);
begin
  in0_1_23 <= std_logic_vector_to_unsigned(in0);
  in1_1_27 <= std_logic_vector_to_unsigned(in1);
  y_2_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(in0_1_23) & unsigned_to_std_logic_vector(in1_1_27));
  y <= unsigned_to_std_logic_vector(y_2_1_concat);
end behavior;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity inverter_b526fbe439 is
  port (
    ip : in std_logic_vector((1 - 1) downto 0);
    op : out std_logic_vector((1 - 1) downto 0);
    clk : in std_logic;
    ce : in std_logic;
    clr : in std_logic);
end inverter_b526fbe439;
architecture behavior of inverter_b526fbe439 is
  signal ip_1_26: unsigned((1 - 1) downto 0);
  type array_type_op_mem_22_20 is array (0 to (1 - 1)) of unsigned((1 - 1) downto 0);
  signal op_mem_22_20: array_type_op_mem_22_20 := (
    0 => "0");
  signal op_mem_22_20_front_din: unsigned((1 - 1) downto 0);
  signal op_mem_22_20_back: unsigned((1 - 1) downto 0);
  signal op_mem_22_20_push_front_pop_back_en: std_logic;
  signal internal_ip_12_1_bitnot: unsigned((1 - 1) downto 0);
begin
  ip_1_26 <= std_logic_vector_to_unsigned(ip);
  op_mem_22_20_back <= op_mem_22_20(0);
  proc_op_mem_22_20: process (clk)
  is
    variable i: integer;
  begin
    if (clk'event and (clk = '1')) then
      if ((ce = '1') and (op_mem_22_20_push_front_pop_back_en = '1')) then
        op_mem_22_20(0) <= op_mem_22_20_front_din;
      end if;
    end if;
  end process proc_op_mem_22_20;
  internal_ip_12_1_bitnot <= std_logic_vector_to_unsigned(not unsigned_to_std_logic_vector(ip_1_26));
  op_mem_22_20_push_front_pop_back_en <= '0';
  op <= unsigned_to_std_logic_vector(internal_ip_12_1_bitnot);
end behavior;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity reinterpret_d4aaa1bdfb is
  port (
    input_port : in std_logic_vector((8 - 1) downto 0);
    output_port : out std_logic_vector((8 - 1) downto 0);
    clk : in std_logic;
    ce : in std_logic;
    clr : in std_logic);
end reinterpret_d4aaa1bdfb;
architecture behavior of reinterpret_d4aaa1bdfb is
  signal input_port_1_40: unsigned((8 - 1) downto 0);
  signal output_port_5_5_force: signed((8 - 1) downto 0);
begin
  input_port_1_40 <= std_logic_vector_to_unsigned(input_port);
  output_port_5_5_force <= unsigned_to_signed(input_port_1_40);
  output_port <= signed_to_std_logic_vector(output_port_5_5_force);
end behavior;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity slice_548b816da1 is
  port (
    x : in std_logic_vector((8 - 1) downto 0);
    y : out std_logic_vector((1 - 1) downto 0);
    clk : in std_logic;
    ce : in std_logic;
    clr : in std_logic);
end slice_548b816da1;
architecture behavior of slice_548b816da1 is
  signal x_1_22: unsigned((8 - 1) downto 0);
  signal y_2_1_slice: unsigned((1 - 1) downto 0);
begin
  x_1_22 <= std_logic_vector_to_unsigned(x);
  y_2_1_slice <= u2u_slice(x_1_22, 7, 7);
  y <= unsigned_to_std_logic_vector(y_2_1_slice);
end behavior;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity slice1_ca2b52d742 is
  port (
    x : in std_logic_vector((8 - 1) downto 0);
    y : out std_logic_vector((7 - 1) downto 0);
    clk : in std_logic;
    ce : in std_logic;
    clr : in std_logic);
end slice1_ca2b52d742;
architecture behavior of slice1_ca2b52d742 is
  signal x_1_22: unsigned((8 - 1) downto 0);
  signal y_2_1_slice: unsigned((7 - 1) downto 0);
begin
  x_1_22 <= std_logic_vector_to_unsigned(x);
  y_2_1_slice <= u2u_slice(x_1_22, 6, 0);
  y <= unsigned_to_std_logic_vector(y_2_1_slice);
end behavior;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity concat_c2ceb1b433 is
  port (
    in0 : in std_logic_vector((1 - 1) downto 0);
    in1 : in std_logic_vector((7 - 1) downto 0);
    y : out std_logic_vector((8 - 1) downto 0);
    clk : in std_logic;
    ce : in std_logic;
    clr : in std_logic);
end concat_c2ceb1b433;
architecture behavior of concat_c2ceb1b433 is
  signal in0_1_23: unsigned((1 - 1) downto 0);
  signal in1_1_27: unsigned((7 - 1) downto 0);
  signal y_2_1_concat: unsigned((8 - 1) downto 0);
begin
  in0_1_23 <= std_logic_vector_to_unsigned(in0);
  in1_1_27 <= std_logic_vector_to_unsigned(in1);
  y_2_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(in0_1_23) & unsigned_to_std_logic_vector(in1_1_27));
  y <= unsigned_to_std_logic_vector(y_2_1_concat);
end behavior;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity inverter_2f02a7b0ae is
  port (
    ip : in std_logic_vector((1 - 1) downto 0);
    op : out std_logic_vector((1 - 1) downto 0);
    clk : in std_logic;
    ce : in std_logic;
    clr : in std_logic);
end inverter_2f02a7b0ae;
architecture behavior of inverter_2f02a7b0ae is
  signal ip_1_26: unsigned((1 - 1) downto 0);
  type array_type_op_mem_22_20 is array (0 to (1 - 1)) of unsigned((1 - 1) downto 0);
  signal op_mem_22_20: array_type_op_mem_22_20 := (
    0 => "0");
  signal op_mem_22_20_front_din: unsigned((1 - 1) downto 0);
  signal op_mem_22_20_back: unsigned((1 - 1) downto 0);
  signal op_mem_22_20_push_front_pop_back_en: std_logic;
  signal internal_ip_12_1_bitnot: unsigned((1 - 1) downto 0);
begin
  ip_1_26 <= std_logic_vector_to_unsigned(ip);
  op_mem_22_20_back <= op_mem_22_20(0);
  proc_op_mem_22_20: process (clk)
  is
    variable i: integer;
  begin
    if (clk'event and (clk = '1')) then
      if ((ce = '1') and (op_mem_22_20_push_front_pop_back_en = '1')) then
        op_mem_22_20(0) <= op_mem_22_20_front_din;
      end if;
    end if;
  end process proc_op_mem_22_20;
  internal_ip_12_1_bitnot <= std_logic_vector_to_unsigned(not unsigned_to_std_logic_vector(ip_1_26));
  op_mem_22_20_push_front_pop_back_en <= '0';
  op <= unsigned_to_std_logic_vector(internal_ip_12_1_bitnot);
end behavior;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity reinterpret_b4b31b4648 is
  port (
    input_port : in std_logic_vector((8 - 1) downto 0);
    output_port : out std_logic_vector((8 - 1) downto 0);
    clk : in std_logic;
    ce : in std_logic;
    clr : in std_logic);
end reinterpret_b4b31b4648;
architecture behavior of reinterpret_b4b31b4648 is
  signal input_port_1_40: unsigned((8 - 1) downto 0);
  signal output_port_5_5_force: signed((8 - 1) downto 0);
begin
  input_port_1_40 <= std_logic_vector_to_unsigned(input_port);
  output_port_5_5_force <= unsigned_to_signed(input_port_1_40);
  output_port <= signed_to_std_logic_vector(output_port_5_5_force);
end behavior;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity slice_1145e8f1a6 is
  port (
    x : in std_logic_vector((8 - 1) downto 0);
    y : out std_logic_vector((1 - 1) downto 0);
    clk : in std_logic;
    ce : in std_logic;
    clr : in std_logic);
end slice_1145e8f1a6;
architecture behavior of slice_1145e8f1a6 is
  signal x_1_22: unsigned((8 - 1) downto 0);
  signal y_2_1_slice: unsigned((1 - 1) downto 0);
begin
  x_1_22 <= std_logic_vector_to_unsigned(x);
  y_2_1_slice <= u2u_slice(x_1_22, 7, 7);
  y <= unsigned_to_std_logic_vector(y_2_1_slice);
end behavior;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity slice1_30272eab40 is
  port (
    x : in std_logic_vector((8 - 1) downto 0);
    y : out std_logic_vector((7 - 1) downto 0);
    clk : in std_logic;
    ce : in std_logic;
    clr : in std_logic);
end slice1_30272eab40;
architecture behavior of slice1_30272eab40 is
  signal x_1_22: unsigned((8 - 1) downto 0);
  signal y_2_1_slice: unsigned((7 - 1) downto 0);
begin
  x_1_22 <= std_logic_vector_to_unsigned(x);
  y_2_1_slice <= u2u_slice(x_1_22, 6, 0);
  y <= unsigned_to_std_logic_vector(y_2_1_slice);
end behavior;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity concat_f31155dc36 is
  port (
    in0 : in std_logic_vector((1 - 1) downto 0);
    in1 : in std_logic_vector((7 - 1) downto 0);
    y : out std_logic_vector((8 - 1) downto 0);
    clk : in std_logic;
    ce : in std_logic;
    clr : in std_logic);
end concat_f31155dc36;
architecture behavior of concat_f31155dc36 is
  signal in0_1_23: unsigned((1 - 1) downto 0);
  signal in1_1_27: unsigned((7 - 1) downto 0);
  signal y_2_1_concat: unsigned((8 - 1) downto 0);
begin
  in0_1_23 <= std_logic_vector_to_unsigned(in0);
  in1_1_27 <= std_logic_vector_to_unsigned(in1);
  y_2_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(in0_1_23) & unsigned_to_std_logic_vector(in1_1_27));
  y <= unsigned_to_std_logic_vector(y_2_1_concat);
end behavior;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity inverter_deb105cfd5 is
  port (
    ip : in std_logic_vector((1 - 1) downto 0);
    op : out std_logic_vector((1 - 1) downto 0);
    clk : in std_logic;
    ce : in std_logic;
    clr : in std_logic);
end inverter_deb105cfd5;
architecture behavior of inverter_deb105cfd5 is
  signal ip_1_26: unsigned((1 - 1) downto 0);
  type array_type_op_mem_22_20 is array (0 to (1 - 1)) of unsigned((1 - 1) downto 0);
  signal op_mem_22_20: array_type_op_mem_22_20 := (
    0 => "0");
  signal op_mem_22_20_front_din: unsigned((1 - 1) downto 0);
  signal op_mem_22_20_back: unsigned((1 - 1) downto 0);
  signal op_mem_22_20_push_front_pop_back_en: std_logic;
  signal internal_ip_12_1_bitnot: unsigned((1 - 1) downto 0);
begin
  ip_1_26 <= std_logic_vector_to_unsigned(ip);
  op_mem_22_20_back <= op_mem_22_20(0);
  proc_op_mem_22_20: process (clk)
  is
    variable i: integer;
  begin
    if (clk'event and (clk = '1')) then
      if ((ce = '1') and (op_mem_22_20_push_front_pop_back_en = '1')) then
        op_mem_22_20(0) <= op_mem_22_20_front_din;
      end if;
    end if;
  end process proc_op_mem_22_20;
  internal_ip_12_1_bitnot <= std_logic_vector_to_unsigned(not unsigned_to_std_logic_vector(ip_1_26));
  op_mem_22_20_push_front_pop_back_en <= '0';
  op <= unsigned_to_std_logic_vector(internal_ip_12_1_bitnot);
end behavior;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity reinterpret_1953f27fdf is
  port (
    input_port : in std_logic_vector((8 - 1) downto 0);
    output_port : out std_logic_vector((8 - 1) downto 0);
    clk : in std_logic;
    ce : in std_logic;
    clr : in std_logic);
end reinterpret_1953f27fdf;
architecture behavior of reinterpret_1953f27fdf is
  signal input_port_1_40: unsigned((8 - 1) downto 0);
  signal output_port_5_5_force: signed((8 - 1) downto 0);
begin
  input_port_1_40 <= std_logic_vector_to_unsigned(input_port);
  output_port_5_5_force <= unsigned_to_signed(input_port_1_40);
  output_port <= signed_to_std_logic_vector(output_port_5_5_force);
end behavior;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity slice_17b71bf882 is
  port (
    x : in std_logic_vector((8 - 1) downto 0);
    y : out std_logic_vector((1 - 1) downto 0);
    clk : in std_logic;
    ce : in std_logic;
    clr : in std_logic);
end slice_17b71bf882;
architecture behavior of slice_17b71bf882 is
  signal x_1_22: unsigned((8 - 1) downto 0);
  signal y_2_1_slice: unsigned((1 - 1) downto 0);
begin
  x_1_22 <= std_logic_vector_to_unsigned(x);
  y_2_1_slice <= u2u_slice(x_1_22, 7, 7);
  y <= unsigned_to_std_logic_vector(y_2_1_slice);
end behavior;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity slice1_b8da15b44a is
  port (
    x : in std_logic_vector((8 - 1) downto 0);
    y : out std_logic_vector((7 - 1) downto 0);
    clk : in std_logic;
    ce : in std_logic;
    clr : in std_logic);
end slice1_b8da15b44a;
architecture behavior of slice1_b8da15b44a is
  signal x_1_22: unsigned((8 - 1) downto 0);
  signal y_2_1_slice: unsigned((7 - 1) downto 0);
begin
  x_1_22 <= std_logic_vector_to_unsigned(x);
  y_2_1_slice <= u2u_slice(x_1_22, 6, 0);
  y <= unsigned_to_std_logic_vector(y_2_1_slice);
end behavior;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity concat_8f2a4bed20 is
  port (
    in0 : in std_logic_vector((1 - 1) downto 0);
    in1 : in std_logic_vector((7 - 1) downto 0);
    y : out std_logic_vector((8 - 1) downto 0);
    clk : in std_logic;
    ce : in std_logic;
    clr : in std_logic);
end concat_8f2a4bed20;
architecture behavior of concat_8f2a4bed20 is
  signal in0_1_23: unsigned((1 - 1) downto 0);
  signal in1_1_27: unsigned((7 - 1) downto 0);
  signal y_2_1_concat: unsigned((8 - 1) downto 0);
begin
  in0_1_23 <= std_logic_vector_to_unsigned(in0);
  in1_1_27 <= std_logic_vector_to_unsigned(in1);
  y_2_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(in0_1_23) & unsigned_to_std_logic_vector(in1_1_27));
  y <= unsigned_to_std_logic_vector(y_2_1_concat);
end behavior;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity inverter_f6278b222a is
  port (
    ip : in std_logic_vector((1 - 1) downto 0);
    op : out std_logic_vector((1 - 1) downto 0);
    clk : in std_logic;
    ce : in std_logic;
    clr : in std_logic);
end inverter_f6278b222a;
architecture behavior of inverter_f6278b222a is
  signal ip_1_26: unsigned((1 - 1) downto 0);
  type array_type_op_mem_22_20 is array (0 to (1 - 1)) of unsigned((1 - 1) downto 0);
  signal op_mem_22_20: array_type_op_mem_22_20 := (
    0 => "0");
  signal op_mem_22_20_front_din: unsigned((1 - 1) downto 0);
  signal op_mem_22_20_back: unsigned((1 - 1) downto 0);
  signal op_mem_22_20_push_front_pop_back_en: std_logic;
  signal internal_ip_12_1_bitnot: unsigned((1 - 1) downto 0);
begin
  ip_1_26 <= std_logic_vector_to_unsigned(ip);
  op_mem_22_20_back <= op_mem_22_20(0);
  proc_op_mem_22_20: process (clk)
  is
    variable i: integer;
  begin
    if (clk'event and (clk = '1')) then
      if ((ce = '1') and (op_mem_22_20_push_front_pop_back_en = '1')) then
        op_mem_22_20(0) <= op_mem_22_20_front_din;
      end if;
    end if;
  end process proc_op_mem_22_20;
  internal_ip_12_1_bitnot <= std_logic_vector_to_unsigned(not unsigned_to_std_logic_vector(ip_1_26));
  op_mem_22_20_push_front_pop_back_en <= '0';
  op <= unsigned_to_std_logic_vector(internal_ip_12_1_bitnot);
end behavior;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity reinterpret_28813488a0 is
  port (
    input_port : in std_logic_vector((8 - 1) downto 0);
    output_port : out std_logic_vector((8 - 1) downto 0);
    clk : in std_logic;
    ce : in std_logic;
    clr : in std_logic);
end reinterpret_28813488a0;
architecture behavior of reinterpret_28813488a0 is
  signal input_port_1_40: unsigned((8 - 1) downto 0);
  signal output_port_5_5_force: signed((8 - 1) downto 0);
begin
  input_port_1_40 <= std_logic_vector_to_unsigned(input_port);
  output_port_5_5_force <= unsigned_to_signed(input_port_1_40);
  output_port <= signed_to_std_logic_vector(output_port_5_5_force);
end behavior;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity slice_4086228a71 is
  port (
    x : in std_logic_vector((8 - 1) downto 0);
    y : out std_logic_vector((1 - 1) downto 0);
    clk : in std_logic;
    ce : in std_logic;
    clr : in std_logic);
end slice_4086228a71;
architecture behavior of slice_4086228a71 is
  signal x_1_22: unsigned((8 - 1) downto 0);
  signal y_2_1_slice: unsigned((1 - 1) downto 0);
begin
  x_1_22 <= std_logic_vector_to_unsigned(x);
  y_2_1_slice <= u2u_slice(x_1_22, 7, 7);
  y <= unsigned_to_std_logic_vector(y_2_1_slice);
end behavior;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity slice1_dc1027beb6 is
  port (
    x : in std_logic_vector((8 - 1) downto 0);
    y : out std_logic_vector((7 - 1) downto 0);
    clk : in std_logic;
    ce : in std_logic;
    clr : in std_logic);
end slice1_dc1027beb6;
architecture behavior of slice1_dc1027beb6 is
  signal x_1_22: unsigned((8 - 1) downto 0);
  signal y_2_1_slice: unsigned((7 - 1) downto 0);
begin
  x_1_22 <= std_logic_vector_to_unsigned(x);
  y_2_1_slice <= u2u_slice(x_1_22, 6, 0);
  y <= unsigned_to_std_logic_vector(y_2_1_slice);
end behavior;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity concat_c6213979ad is
  port (
    in0 : in std_logic_vector((1 - 1) downto 0);
    in1 : in std_logic_vector((7 - 1) downto 0);
    y : out std_logic_vector((8 - 1) downto 0);
    clk : in std_logic;
    ce : in std_logic;
    clr : in std_logic);
end concat_c6213979ad;
architecture behavior of concat_c6213979ad is
  signal in0_1_23: unsigned((1 - 1) downto 0);
  signal in1_1_27: unsigned((7 - 1) downto 0);
  signal y_2_1_concat: unsigned((8 - 1) downto 0);
begin
  in0_1_23 <= std_logic_vector_to_unsigned(in0);
  in1_1_27 <= std_logic_vector_to_unsigned(in1);
  y_2_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(in0_1_23) & unsigned_to_std_logic_vector(in1_1_27));
  y <= unsigned_to_std_logic_vector(y_2_1_concat);
end behavior;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity inverter_14e3210e70 is
  port (
    ip : in std_logic_vector((1 - 1) downto 0);
    op : out std_logic_vector((1 - 1) downto 0);
    clk : in std_logic;
    ce : in std_logic;
    clr : in std_logic);
end inverter_14e3210e70;
architecture behavior of inverter_14e3210e70 is
  signal ip_1_26: unsigned((1 - 1) downto 0);
  type array_type_op_mem_22_20 is array (0 to (1 - 1)) of unsigned((1 - 1) downto 0);
  signal op_mem_22_20: array_type_op_mem_22_20 := (
    0 => "0");
  signal op_mem_22_20_front_din: unsigned((1 - 1) downto 0);
  signal op_mem_22_20_back: unsigned((1 - 1) downto 0);
  signal op_mem_22_20_push_front_pop_back_en: std_logic;
  signal internal_ip_12_1_bitnot: unsigned((1 - 1) downto 0);
begin
  ip_1_26 <= std_logic_vector_to_unsigned(ip);
  op_mem_22_20_back <= op_mem_22_20(0);
  proc_op_mem_22_20: process (clk)
  is
    variable i: integer;
  begin
    if (clk'event and (clk = '1')) then
      if ((ce = '1') and (op_mem_22_20_push_front_pop_back_en = '1')) then
        op_mem_22_20(0) <= op_mem_22_20_front_din;
      end if;
    end if;
  end process proc_op_mem_22_20;
  internal_ip_12_1_bitnot <= std_logic_vector_to_unsigned(not unsigned_to_std_logic_vector(ip_1_26));
  op_mem_22_20_push_front_pop_back_en <= '0';
  op <= unsigned_to_std_logic_vector(internal_ip_12_1_bitnot);
end behavior;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity reinterpret_c607a35a29 is
  port (
    input_port : in std_logic_vector((8 - 1) downto 0);
    output_port : out std_logic_vector((8 - 1) downto 0);
    clk : in std_logic;
    ce : in std_logic;
    clr : in std_logic);
end reinterpret_c607a35a29;
architecture behavior of reinterpret_c607a35a29 is
  signal input_port_1_40: unsigned((8 - 1) downto 0);
  signal output_port_5_5_force: signed((8 - 1) downto 0);
begin
  input_port_1_40 <= std_logic_vector_to_unsigned(input_port);
  output_port_5_5_force <= unsigned_to_signed(input_port_1_40);
  output_port <= signed_to_std_logic_vector(output_port_5_5_force);
end behavior;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity slice_d1e6bddb3b is
  port (
    x : in std_logic_vector((8 - 1) downto 0);
    y : out std_logic_vector((1 - 1) downto 0);
    clk : in std_logic;
    ce : in std_logic;
    clr : in std_logic);
end slice_d1e6bddb3b;
architecture behavior of slice_d1e6bddb3b is
  signal x_1_22: unsigned((8 - 1) downto 0);
  signal y_2_1_slice: unsigned((1 - 1) downto 0);
begin
  x_1_22 <= std_logic_vector_to_unsigned(x);
  y_2_1_slice <= u2u_slice(x_1_22, 7, 7);
  y <= unsigned_to_std_logic_vector(y_2_1_slice);
end behavior;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity slice1_c85fcf892b is
  port (
    x : in std_logic_vector((8 - 1) downto 0);
    y : out std_logic_vector((7 - 1) downto 0);
    clk : in std_logic;
    ce : in std_logic;
    clr : in std_logic);
end slice1_c85fcf892b;
architecture behavior of slice1_c85fcf892b is
  signal x_1_22: unsigned((8 - 1) downto 0);
  signal y_2_1_slice: unsigned((7 - 1) downto 0);
begin
  x_1_22 <= std_logic_vector_to_unsigned(x);
  y_2_1_slice <= u2u_slice(x_1_22, 6, 0);
  y <= unsigned_to_std_logic_vector(y_2_1_slice);
end behavior;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity concat_abceb0e700 is
  port (
    in0 : in std_logic_vector((1 - 1) downto 0);
    in1 : in std_logic_vector((7 - 1) downto 0);
    y : out std_logic_vector((8 - 1) downto 0);
    clk : in std_logic;
    ce : in std_logic;
    clr : in std_logic);
end concat_abceb0e700;
architecture behavior of concat_abceb0e700 is
  signal in0_1_23: unsigned((1 - 1) downto 0);
  signal in1_1_27: unsigned((7 - 1) downto 0);
  signal y_2_1_concat: unsigned((8 - 1) downto 0);
begin
  in0_1_23 <= std_logic_vector_to_unsigned(in0);
  in1_1_27 <= std_logic_vector_to_unsigned(in1);
  y_2_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(in0_1_23) & unsigned_to_std_logic_vector(in1_1_27));
  y <= unsigned_to_std_logic_vector(y_2_1_concat);
end behavior;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity inverter_1583af95f1 is
  port (
    ip : in std_logic_vector((1 - 1) downto 0);
    op : out std_logic_vector((1 - 1) downto 0);
    clk : in std_logic;
    ce : in std_logic;
    clr : in std_logic);
end inverter_1583af95f1;
architecture behavior of inverter_1583af95f1 is
  signal ip_1_26: unsigned((1 - 1) downto 0);
  type array_type_op_mem_22_20 is array (0 to (1 - 1)) of unsigned((1 - 1) downto 0);
  signal op_mem_22_20: array_type_op_mem_22_20 := (
    0 => "0");
  signal op_mem_22_20_front_din: unsigned((1 - 1) downto 0);
  signal op_mem_22_20_back: unsigned((1 - 1) downto 0);
  signal op_mem_22_20_push_front_pop_back_en: std_logic;
  signal internal_ip_12_1_bitnot: unsigned((1 - 1) downto 0);
begin
  ip_1_26 <= std_logic_vector_to_unsigned(ip);
  op_mem_22_20_back <= op_mem_22_20(0);
  proc_op_mem_22_20: process (clk)
  is
    variable i: integer;
  begin
    if (clk'event and (clk = '1')) then
      if ((ce = '1') and (op_mem_22_20_push_front_pop_back_en = '1')) then
        op_mem_22_20(0) <= op_mem_22_20_front_din;
      end if;
    end if;
  end process proc_op_mem_22_20;
  internal_ip_12_1_bitnot <= std_logic_vector_to_unsigned(not unsigned_to_std_logic_vector(ip_1_26));
  op_mem_22_20_push_front_pop_back_en <= '0';
  op <= unsigned_to_std_logic_vector(internal_ip_12_1_bitnot);
end behavior;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity reinterpret_7eef37775d is
  port (
    input_port : in std_logic_vector((8 - 1) downto 0);
    output_port : out std_logic_vector((8 - 1) downto 0);
    clk : in std_logic;
    ce : in std_logic;
    clr : in std_logic);
end reinterpret_7eef37775d;
architecture behavior of reinterpret_7eef37775d is
  signal input_port_1_40: unsigned((8 - 1) downto 0);
  signal output_port_5_5_force: signed((8 - 1) downto 0);
begin
  input_port_1_40 <= std_logic_vector_to_unsigned(input_port);
  output_port_5_5_force <= unsigned_to_signed(input_port_1_40);
  output_port <= signed_to_std_logic_vector(output_port_5_5_force);
end behavior;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity slice_58a5b34657 is
  port (
    x : in std_logic_vector((8 - 1) downto 0);
    y : out std_logic_vector((1 - 1) downto 0);
    clk : in std_logic;
    ce : in std_logic;
    clr : in std_logic);
end slice_58a5b34657;
architecture behavior of slice_58a5b34657 is
  signal x_1_22: unsigned((8 - 1) downto 0);
  signal y_2_1_slice: unsigned((1 - 1) downto 0);
begin
  x_1_22 <= std_logic_vector_to_unsigned(x);
  y_2_1_slice <= u2u_slice(x_1_22, 7, 7);
  y <= unsigned_to_std_logic_vector(y_2_1_slice);
end behavior;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity slice1_94a4a96ba5 is
  port (
    x : in std_logic_vector((8 - 1) downto 0);
    y : out std_logic_vector((7 - 1) downto 0);
    clk : in std_logic;
    ce : in std_logic;
    clr : in std_logic);
end slice1_94a4a96ba5;
architecture behavior of slice1_94a4a96ba5 is
  signal x_1_22: unsigned((8 - 1) downto 0);
  signal y_2_1_slice: unsigned((7 - 1) downto 0);
begin
  x_1_22 <= std_logic_vector_to_unsigned(x);
  y_2_1_slice <= u2u_slice(x_1_22, 6, 0);
  y <= unsigned_to_std_logic_vector(y_2_1_slice);
end behavior;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity concat_c79d543ed9 is
  port (
    in0 : in std_logic_vector((1 - 1) downto 0);
    in1 : in std_logic_vector((7 - 1) downto 0);
    y : out std_logic_vector((8 - 1) downto 0);
    clk : in std_logic;
    ce : in std_logic;
    clr : in std_logic);
end concat_c79d543ed9;
architecture behavior of concat_c79d543ed9 is
  signal in0_1_23: unsigned((1 - 1) downto 0);
  signal in1_1_27: unsigned((7 - 1) downto 0);
  signal y_2_1_concat: unsigned((8 - 1) downto 0);
begin
  in0_1_23 <= std_logic_vector_to_unsigned(in0);
  in1_1_27 <= std_logic_vector_to_unsigned(in1);
  y_2_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(in0_1_23) & unsigned_to_std_logic_vector(in1_1_27));
  y <= unsigned_to_std_logic_vector(y_2_1_concat);
end behavior;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity inverter_8ce249e4c9 is
  port (
    ip : in std_logic_vector((1 - 1) downto 0);
    op : out std_logic_vector((1 - 1) downto 0);
    clk : in std_logic;
    ce : in std_logic;
    clr : in std_logic);
end inverter_8ce249e4c9;
architecture behavior of inverter_8ce249e4c9 is
  signal ip_1_26: unsigned((1 - 1) downto 0);
  type array_type_op_mem_22_20 is array (0 to (1 - 1)) of unsigned((1 - 1) downto 0);
  signal op_mem_22_20: array_type_op_mem_22_20 := (
    0 => "0");
  signal op_mem_22_20_front_din: unsigned((1 - 1) downto 0);
  signal op_mem_22_20_back: unsigned((1 - 1) downto 0);
  signal op_mem_22_20_push_front_pop_back_en: std_logic;
  signal internal_ip_12_1_bitnot: unsigned((1 - 1) downto 0);
begin
  ip_1_26 <= std_logic_vector_to_unsigned(ip);
  op_mem_22_20_back <= op_mem_22_20(0);
  proc_op_mem_22_20: process (clk)
  is
    variable i: integer;
  begin
    if (clk'event and (clk = '1')) then
      if ((ce = '1') and (op_mem_22_20_push_front_pop_back_en = '1')) then
        op_mem_22_20(0) <= op_mem_22_20_front_din;
      end if;
    end if;
  end process proc_op_mem_22_20;
  internal_ip_12_1_bitnot <= std_logic_vector_to_unsigned(not unsigned_to_std_logic_vector(ip_1_26));
  op_mem_22_20_push_front_pop_back_en <= '0';
  op <= unsigned_to_std_logic_vector(internal_ip_12_1_bitnot);
end behavior;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity reinterpret_955f8abbef is
  port (
    input_port : in std_logic_vector((8 - 1) downto 0);
    output_port : out std_logic_vector((8 - 1) downto 0);
    clk : in std_logic;
    ce : in std_logic;
    clr : in std_logic);
end reinterpret_955f8abbef;
architecture behavior of reinterpret_955f8abbef is
  signal input_port_1_40: unsigned((8 - 1) downto 0);
  signal output_port_5_5_force: signed((8 - 1) downto 0);
begin
  input_port_1_40 <= std_logic_vector_to_unsigned(input_port);
  output_port_5_5_force <= unsigned_to_signed(input_port_1_40);
  output_port <= signed_to_std_logic_vector(output_port_5_5_force);
end behavior;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity slice_510bfcefde is
  port (
    x : in std_logic_vector((8 - 1) downto 0);
    y : out std_logic_vector((1 - 1) downto 0);
    clk : in std_logic;
    ce : in std_logic;
    clr : in std_logic);
end slice_510bfcefde;
architecture behavior of slice_510bfcefde is
  signal x_1_22: unsigned((8 - 1) downto 0);
  signal y_2_1_slice: unsigned((1 - 1) downto 0);
begin
  x_1_22 <= std_logic_vector_to_unsigned(x);
  y_2_1_slice <= u2u_slice(x_1_22, 7, 7);
  y <= unsigned_to_std_logic_vector(y_2_1_slice);
end behavior;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity slice1_a788d95eec is
  port (
    x : in std_logic_vector((8 - 1) downto 0);
    y : out std_logic_vector((7 - 1) downto 0);
    clk : in std_logic;
    ce : in std_logic;
    clr : in std_logic);
end slice1_a788d95eec;
architecture behavior of slice1_a788d95eec is
  signal x_1_22: unsigned((8 - 1) downto 0);
  signal y_2_1_slice: unsigned((7 - 1) downto 0);
begin
  x_1_22 <= std_logic_vector_to_unsigned(x);
  y_2_1_slice <= u2u_slice(x_1_22, 6, 0);
  y <= unsigned_to_std_logic_vector(y_2_1_slice);
end behavior;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity convert_func_call is
    generic (
        din_width    : integer := 16;
        din_bin_pt   : integer := 4;
        din_arith    : integer := xlUnsigned;
        dout_width   : integer := 8;
        dout_bin_pt  : integer := 2;
        dout_arith   : integer := xlUnsigned;
        quantization : integer := xlTruncate;
        overflow     : integer := xlWrap);
    port (
        din : in std_logic_vector (din_width-1 downto 0);
        result : out std_logic_vector (dout_width-1 downto 0));
end convert_func_call;
architecture behavior of convert_func_call is
begin
    result <= convert_type(din, din_width, din_bin_pt, din_arith,
                           dout_width, dout_bin_pt, dout_arith,
                           quantization, overflow);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity xlconvert is
    generic (
        din_width    : integer := 16;
        din_bin_pt   : integer := 4;
        din_arith    : integer := xlUnsigned;
        dout_width   : integer := 8;
        dout_bin_pt  : integer := 2;
        dout_arith   : integer := xlUnsigned;
        bool_conversion : integer :=0;
        latency      : integer := 0;
        quantization : integer := xlTruncate;
        overflow     : integer := xlWrap);
    port (
        din : in std_logic_vector (din_width-1 downto 0);
        ce  : in std_logic;
        clr : in std_logic;
        clk : in std_logic;
        dout : out std_logic_vector (dout_width-1 downto 0));
end xlconvert;
architecture behavior of xlconvert is
    component synth_reg
        generic (width       : integer;
                 latency     : integer);
        port (i           : in std_logic_vector(width-1 downto 0);
              ce      : in std_logic;
              clr     : in std_logic;
              clk     : in std_logic;
              o       : out std_logic_vector(width-1 downto 0));
    end component;
    component convert_func_call
        generic (
            din_width    : integer := 16;
            din_bin_pt   : integer := 4;
            din_arith    : integer := xlUnsigned;
            dout_width   : integer := 8;
            dout_bin_pt  : integer := 2;
            dout_arith   : integer := xlUnsigned;
            quantization : integer := xlTruncate;
            overflow     : integer := xlWrap);
        port (
            din : in std_logic_vector (din_width-1 downto 0);
            result : out std_logic_vector (dout_width-1 downto 0));
    end component;
    -- synopsys translate_off
    signal real_din, real_dout : real;
    -- synopsys translate_on
    signal result : std_logic_vector(dout_width-1 downto 0);
begin
    -- synopsys translate_off
    -- synopsys translate_on
    bool_conversion_generate : if (bool_conversion = 1)
    generate
      result <= din;
    end generate;
    std_conversion_generate : if (bool_conversion = 0)
    generate
      convert : convert_func_call
        generic map (
          din_width   => din_width,
          din_bin_pt  => din_bin_pt,
          din_arith   => din_arith,
          dout_width  => dout_width,
          dout_bin_pt => dout_bin_pt,
          dout_arith  => dout_arith,
          quantization => quantization,
          overflow     => overflow)
        port map (
          din => din,
          result => result);
    end generate;
    latency_test : if (latency > 0)
    generate
        reg : synth_reg
            generic map ( width => dout_width,
                          latency => latency)
            port map (i => result,
                      ce => ce,
                      clr => clr,
                      clk => clk,
                      o => dout);
    end generate;
    latency0 : if (latency = 0)
    generate
        dout <= result;
    end generate latency0;
end  behavior;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
-- synopsys translate_off
library XilinxCoreLib;
-- synopsys translate_on
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.conv_pkg.all;
entity xladdsub is
  generic (
    core_name0: string := "";
    a_width: integer := 16;
    a_bin_pt: integer := 4;
    a_arith: integer := xlUnsigned;
    c_in_width: integer := 16;
    c_in_bin_pt: integer := 4;
    c_in_arith: integer := xlUnsigned;
    c_out_width: integer := 16;
    c_out_bin_pt: integer := 4;
    c_out_arith: integer := xlUnsigned;
    b_width: integer := 8;
    b_bin_pt: integer := 2;
    b_arith: integer := xlUnsigned;
    s_width: integer := 17;
    s_bin_pt: integer := 4;
    s_arith: integer := xlUnsigned;
    rst_width: integer := 1;
    rst_bin_pt: integer := 0;
    rst_arith: integer := xlUnsigned;
    en_width: integer := 1;
    en_bin_pt: integer := 0;
    en_arith: integer := xlUnsigned;
    full_s_width: integer := 17;
    full_s_arith: integer := xlUnsigned;
    mode: integer := xlAddMode;
    extra_registers: integer := 0;
    latency: integer := 0;
    quantization: integer := xlTruncate;
    overflow: integer := xlWrap;
    c_latency: integer := 0;
    c_output_width: integer := 17;
    c_has_q : integer := 1;
    c_has_s : integer := 0;
    c_has_c_out : integer := 0;
    c_has_q_c_out : integer := 0;
    c_has_b_out : integer := 0;
    c_has_q_b_out : integer := 0;
    c_has_q_ovfl : integer := 0;
    c_has_ovfl : integer := 0
  );
  port (
    a: in std_logic_vector(a_width - 1 downto 0);
    b: in std_logic_vector(b_width - 1 downto 0);
    c_in : in std_logic_vector (0 downto 0) := "0";
    ce: in std_logic;
    clr: in std_logic := '0';
    clk: in std_logic;
    rst: in std_logic_vector(rst_width - 1 downto 0) := "0";
    en: in std_logic_vector(en_width - 1 downto 0) := "1";
    c_out : out std_logic_vector (0 downto 0);
    s: out std_logic_vector(s_width - 1 downto 0)
  );
end xladdsub ;
architecture behavior of xladdsub is

  component synth_reg
    generic (
      width: integer := 16;
      latency: integer := 5
    );
    port (
      i: in std_logic_vector(width - 1 downto 0);
      ce: in std_logic;
      clr: in std_logic;
      clk: in std_logic;
      o: out std_logic_vector(width - 1 downto 0)
    );
  end component;
  function format_input(inp: std_logic_vector; old_width, delta, new_arith,
                        new_width: integer)
    return std_logic_vector
  is
    variable vec: std_logic_vector(old_width-1 downto 0);
    variable padded_inp: std_logic_vector((old_width + delta)-1  downto 0);
    variable result: std_logic_vector(new_width-1 downto 0);
  begin
    vec := inp;
    if delta > 0 then
      padded_inp := pad_LSB(vec, old_width+delta);
      result := extend_MSB(padded_inp, new_width, new_arith);
    else
      result := extend_MSB(vec, new_width, new_arith);
    end if;
    return result;
  end;
  constant full_s_bin_pt: integer := fractional_bits(a_bin_pt, b_bin_pt);
  constant full_a_width: integer := full_s_width;
  constant full_b_width: integer := full_s_width;
  signal full_a: std_logic_vector(full_a_width - 1 downto 0);
  signal full_b: std_logic_vector(full_b_width - 1 downto 0);
  signal core_s: std_logic_vector(full_s_width - 1 downto 0);
  signal conv_s: std_logic_vector(s_width - 1 downto 0);
  signal temp_cout : std_logic;
  signal internal_clr: std_logic;
  signal internal_ce: std_logic;
  signal extra_reg_ce: std_logic;
  signal override: std_logic;
  signal logic1: std_logic_vector(0 downto 0);
  component adder_subtracter_virtex2p_7_0_23d84c584623d65e
    port (
      a: in std_logic_vector( 33 - 1 downto 0);
      clk: in std_logic:= '0';
      ce: in std_logic:= '0';
      q: out std_logic_vector(c_output_width - 1 downto 0);
      b: in std_logic_vector(33 - 1 downto 0)
    );
  end component;
  attribute syn_black_box of adder_subtracter_virtex2p_7_0_23d84c584623d65e:
    component is true;
  attribute fpga_dont_touch of adder_subtracter_virtex2p_7_0_23d84c584623d65e:
    component is "true";
  attribute box_type of adder_subtracter_virtex2p_7_0_23d84c584623d65e:
    component  is "black_box";
begin
  internal_clr <= (clr or (rst(0))) and ce;
  internal_ce <= ce and en(0);
  logic1(0) <= '1';
  addsub_process: process(a, b, core_s)
  begin
    full_a <= format_input(a, a_width, b_bin_pt - a_bin_pt, a_arith,
                           full_a_width);
    full_b <= format_input(b, b_width, a_bin_pt - b_bin_pt, b_arith,
                           full_b_width);
    conv_s <= convert_type(core_s, full_s_width, full_s_bin_pt, full_s_arith,
                           s_width, s_bin_pt, s_arith, quantization, overflow);
  end process addsub_process;

  comp0: if ((core_name0 = "adder_subtracter_virtex2p_7_0_23d84c584623d65e")) generate
    core_instance0: adder_subtracter_virtex2p_7_0_23d84c584623d65e
      port map (
        a => full_a,
        clk => clk,
        ce => internal_ce,
        q => core_s,
        b => full_b
      );
  end generate;
  latency_test: if (extra_registers > 0) generate
      override_test: if (c_latency > 1) generate
       override_pipe: synth_reg
          generic map (
            width => 1,
            latency => c_latency)
          port map (
            i => logic1,
            ce => internal_ce,
            clr => internal_clr,
            clk => clk,
            o(0) => override);
       extra_reg_ce <= ce and en(0) and override;
      end generate override_test;
      no_override: if (c_latency = 0) or (c_latency = 1) generate
       extra_reg_ce <= ce and en(0);
      end generate no_override;
      extra_reg: synth_reg
        generic map (
          width => s_width,
          latency => extra_registers
        )
        port map (
          i => conv_s,
          ce => extra_reg_ce,
          clr => internal_clr,
          clk => clk,
          o => s
        );
      cout_test : if((c_has_c_out = 1) or
                (c_has_b_out = 1) or
                (c_has_q_c_out = 1) or
                (c_has_q_b_out = 1)) generate
      c_out_extra_reg: synth_reg
        generic map (
          width => 1,
          latency => extra_registers
        )
        port map (
          i(0) => temp_cout,
          ce => extra_reg_ce,
          clr => internal_clr,
          clk => clk,
          o => c_out
        );
      end generate cout_test;
  end generate;
  latency_s: if  ((latency = 0) or (extra_registers = 0))  generate
    s <= conv_s;
  end generate latency_s;
  latency0: if ( ((latency = 0) or (extra_registers = 0)) and
                ((c_has_b_out = 1) or
                (c_has_q_c_out = 1) or
                (c_has_c_out = 1) or
                (c_has_q_b_out = 1)))  generate
    c_out(0) <= temp_cout;
  end generate latency0;
  tie_dangling_cout: if ((c_has_c_out = 0) and
                        (c_has_b_out = 0) and
                        (c_has_q_c_out = 0) and
                        (c_has_q_b_out = 0)) generate
    c_out <= "0";
  end generate tie_dangling_cout;
end architecture behavior;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity constant1_2ba2b4f03c is
  port (
    op : out std_logic_vector((1 - 1) downto 0);
    clk : in std_logic;
    ce : in std_logic;
    clr : in std_logic);
end constant1_2ba2b4f03c;
architecture behavior of constant1_2ba2b4f03c is
begin
  op <= "0";
end behavior;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity constant2_a7a5800303 is
  port (
    op : out std_logic_vector((1 - 1) downto 0);
    clk : in std_logic;
    ce : in std_logic;
    clr : in std_logic);
end constant2_a7a5800303;
architecture behavior of constant2_a7a5800303 is
begin
  op <= "1";
end behavior;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity constant3_2994ece7ca is
  port (
    op : out std_logic_vector((10 - 1) downto 0);
    clk : in std_logic;
    ce : in std_logic;
    clr : in std_logic);
end constant3_2994ece7ca;
architecture behavior of constant3_2994ece7ca is
begin
  op <= "0000000000";
end behavior;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity constant4_ad9ae8727a is
  port (
    op : out std_logic_vector((1 - 1) downto 0);
    clk : in std_logic;
    ce : in std_logic;
    clr : in std_logic);
end constant4_ad9ae8727a;
architecture behavior of constant4_ad9ae8727a is
begin
  op <= "1";
end behavior;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity constant5_f77e6e4b80 is
  port (
    op : out std_logic_vector((1 - 1) downto 0);
    clk : in std_logic;
    ce : in std_logic;
    clr : in std_logic);
end constant5_f77e6e4b80;
architecture behavior of constant5_f77e6e4b80 is
begin
  op <= "0";
end behavior;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity constant6_4c5259419a is
  port (
    op : out std_logic_vector((10 - 1) downto 0);
    clk : in std_logic;
    ce : in std_logic;
    clr : in std_logic);
end constant6_4c5259419a;
architecture behavior of constant6_4c5259419a is
begin
  op <= "0000000001";
end behavior;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity constant7_5a759dc8e0 is
  port (
    op : out std_logic_vector((1 - 1) downto 0);
    clk : in std_logic;
    ce : in std_logic;
    clr : in std_logic);
end constant7_5a759dc8e0;
architecture behavior of constant7_5a759dc8e0 is
begin
  op <= "1";
end behavior;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity constant8_738ac8f738 is
  port (
    op : out std_logic_vector((6 - 1) downto 0);
    clk : in std_logic;
    ce : in std_logic;
    clr : in std_logic);
end constant8_738ac8f738;
architecture behavior of constant8_738ac8f738 is
begin
  op <= "000000";
end behavior;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity constant9_7040000009 is
  port (
    op : out std_logic_vector((6 - 1) downto 0);
    clk : in std_logic;
    ce : in std_logic;
    clr : in std_logic);
end constant9_7040000009;
architecture behavior of constant9_7040000009 is
begin
  op <= "000000";
end behavior;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity logical_093b0449cf is
  port (
    d0 : in std_logic_vector((1 - 1) downto 0);
    d1 : in std_logic_vector((1 - 1) downto 0);
    d2 : in std_logic_vector((1 - 1) downto 0);
    d3 : in std_logic_vector((1 - 1) downto 0);
    y : out std_logic_vector((1 - 1) downto 0);
    clk : in std_logic;
    ce : in std_logic;
    clr : in std_logic);
end logical_093b0449cf;
architecture behavior of logical_093b0449cf is
  signal d0_1_24: boolean;
  signal d1_1_27: boolean;
  signal d2_1_30: boolean;
  signal d3_1_33: boolean;
  type array_type_latency_pipe_5_26 is array (0 to (1 - 1)) of boolean;
  signal latency_pipe_5_26: array_type_latency_pipe_5_26 := (
    0 => false);
  signal latency_pipe_5_26_front_din: boolean;
  signal latency_pipe_5_26_back: boolean;
  signal latency_pipe_5_26_push_front_pop_back_en: std_logic;
  signal fully_2_1_bit: boolean;
begin
  d0_1_24 <= ((d0) = "1");
  d1_1_27 <= ((d1) = "1");
  d2_1_30 <= ((d2) = "1");
  d3_1_33 <= ((d3) = "1");
  latency_pipe_5_26_back <= latency_pipe_5_26(0);
  proc_latency_pipe_5_26: process (clk)
  is
    variable i: integer;
  begin
    if (clk'event and (clk = '1')) then
      if ((ce = '1') and (latency_pipe_5_26_push_front_pop_back_en = '1')) then
        latency_pipe_5_26(0) <= latency_pipe_5_26_front_din;
      end if;
    end if;
  end process proc_latency_pipe_5_26;
  fully_2_1_bit <= ((boolean_to_vector(d0_1_24) or boolean_to_vector(d1_1_27) or boolean_to_vector(d2_1_30) or boolean_to_vector(d3_1_33)) = "1");
  latency_pipe_5_26_front_din <= fully_2_1_bit;
  latency_pipe_5_26_push_front_pop_back_en <= '1';
  y <= boolean_to_vector(latency_pipe_5_26_back);
end behavior;
----------------------------------------------------------------------------------
-- bitreducer8to2 - Behavioral 
--
-- Input a set of four parallel 8-bit samples. Here 's0' is the oldest and 
-- 's3' the newest sample in a time series.
--
-- These samples will be converted into two-bit data and placed into a byte, 
-- the first/oldest sample is placed into the MSB of the byte.
--
-- Eight such bytes are gathered into a 64-bit word. Again the oldest samples
-- will be found in the MSB of the 64-bit word. The output contains 32 samples.
-- No decimation.
--
-- The sync signal is propagated through the block. The magnitude levels
-- are specified externally. This way software can perform "AGC" control to
-- provide a 17%-33%-33%-17% histogram distribution for 11/10/00/01 samples
-- respectively.
--
-- Encoding is per Mk4 Correlator Chip encoding:
--    [thresh..inf]   : 01
--    [0..thresh[     : 00
--    [-thresh..0[    : 10
--    [-inf..-thresh[ : 11
-- A smarter twos complement encoding would be possible:
--    [thresh..inf]   : 01
--    [0..thresh[     : 00
--    [-thresh..0[    : 11
--    [-inf..-thresh[ : 10
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- use ieee.std_logic_signed.all; -- signed samples
use ieee.numeric_std.all;

entity bitreducer8to2_v10 is
    port ( 
        clk : in std_logic;
        ce  : in std_logic;
        rst : in std_logic;

        -- 8-bit samples
        s0       : in std_logic_vector(7 downto 0);
        s1       : in std_logic_vector(7 downto 0);
        s2       : in std_logic_vector(7 downto 0);
        s3       : in std_logic_vector(7 downto 0);
        valid_in : in std_logic;
        sync_in  : in std_logic;

        -- threshold/AGC
        magnitude_level_pos : in std_logic_vector(7 downto 0); -- must be positive
        magnitude_level_neg : in std_logic_vector(7 downto 0); -- must be negative
        
        -- 32 concatenated 2-bit samples
        samples   : out std_logic_vector(63 downto 0) := (others=>'0');
        valid_out : out std_logic := '0';
        syncs_out : out std_logic_vector(7 downto 0) := (others=>'0');
        sync_out  : out std_logic := '0'
	);
end bitreducer8to2_v10;

architecture Behavioral of bitreducer8to2_v10 is

    -- first stage: 8 to 2 bit reduction: four bytes in, one byte out
    signal sm_valid : std_logic;
    signal sm_sync  : std_logic;
    signal s0_sign  : std_logic;
    signal s1_sign  : std_logic;
    signal s2_sign  : std_logic;
    signal s3_sign  : std_logic;
    signal s0_mag   : std_logic;
    signal s1_mag   : std_logic;
    signal s2_mag   : std_logic;
    signal s3_mag   : std_logic;
    
    signal magnitude_level_pos_1 : std_logic_vector(7 downto 0);
    signal magnitude_level_neg_1 : std_logic_vector(7 downto 0);       
    
    -- second stage: assemble eight of the previous stage bytes to one 64-bit output word
    signal shifter       : std_logic_vector(63 downto 0) := (others=>'0');
    signal shifter_valid : std_logic := '0';
    signal shifter_syncs : std_logic_vector(7 downto 0) := (others=>'0');

    -- final stage: static copy of a completed output vector
    signal output_l       : std_logic_vector(63 downto 0) := (others=>'0');
    signal output_valid_l : std_logic := '0';
    signal output_syncs_l : std_logic_vector(7 downto 0) := (others=>'0');
    signal output_sync_l  : std_logic := '0';
    
begin

    -- first stage: "AGC"
    agc_proc: process(clk)
    begin
        if rising_edge(clk) then
            magnitude_level_pos_1 <= magnitude_level_pos;
            magnitude_level_neg_1 <= magnitude_level_neg;        
            sm_valid <= valid_in;
            sm_sync <= sync_in;
            s0_sign <= s0(7);
            s1_sign <= s1(7);
            s2_sign <= s2(7);
            s3_sign <= s3(7);
            if (signed(s0) >= signed(magnitude_level_pos_1) or signed(s0) <= signed(magnitude_level_neg_1)) then
                s0_mag <= '1';
            else
                s0_mag <= '0';
            end if;
            if (signed(s1) >= signed(magnitude_level_pos_1) or signed(s1) <= signed(magnitude_level_neg_1)) then
                s1_mag <= '1';
            else
                s1_mag <= '0';
            end if;
            if (signed(s2) >= signed(magnitude_level_pos_1) or signed(s2) <= signed(magnitude_level_neg_1)) then
                s2_mag <= '1';
            else
                s2_mag <= '0';
            end if;
            if (signed(s3) >= signed(magnitude_level_pos_1) or signed(s3) <= signed(magnitude_level_neg_1)) then
                s3_mag <= '1';
            else
                s3_mag <= '0';
            end if;
        end if;
    end process;
    
    -- second stage: "compacting" and output
    compactor_proc: process(clk, rst)
        variable bytes_added_v : integer range 0 to 7;
        variable signal_ready_v : std_logic;
    begin
        if rising_edge(clk) then
            if (rst = '1') then
                bytes_added_v := 0;
                signal_ready_v := '0';
                shifter <= (others=>'0');
                shifter_valid <= '0';
                shifter_syncs <= (others=>'0');
            else
                if (sm_valid = '1') then
                    -- oldest sample will be found in the MSB of the first byte
                    --   t[0] t[1] t[2] t[3] | t[4] t[5] t[6] t[7] | ... | t[28] t[29] t[30] t[31]
                    -- however VDIF wants 2 x 32-bit words with {t[15] ... t[0] | t[31] ... t[16])
                    -- and that is still a TODO
                    shifter_syncs <= shifter_syncs(6 downto 0) & sm_sync;
                    shifter <= shifter(55 downto 0)
                            & s0_sign & s0_mag
                            & s1_sign & s1_mag
                            & s2_sign & s2_mag
                            & s3_sign & s3_mag ;
                    if (bytes_added_v = 7) then
                        bytes_added_v := 0;
                        signal_ready_v := '1';
                    else
                        bytes_added_v := bytes_added_v + 1;
                    end if;
                end if;
                if (signal_ready_v = '1') then
                    signal_ready_v := '0';
                    shifter_valid <= '1';
                else
                    shifter_valid <= '0';
                end if;
            end if;
        end if;
    end process;

    -- last stage: output
    output_proc: process(clk, rst)
    begin
        if rising_edge(clk) then
            if (rst = '1') then
                output_l <= (others=>'0');
                output_syncs_l <= (others=>'0');
                output_sync_l <= '0';
                output_valid_l <= '0';
            else
                if (shifter_valid = '1') then
                    output_l <= shifter;
                    output_syncs_l <= shifter_syncs;
                    if (shifter_syncs = "00000000") then
                        output_sync_l <= '0';
                    else
                        output_sync_l <= '1';
                    end if;
                end if;
                output_valid_l <= shifter_valid;
            end if;
        end if;
    end process;

    -- copy
    samples <= output_l;
    valid_out <= output_valid_l;
    syncs_out <= output_syncs_l;
    sync_out <= '1' when (output_sync_l = '1' and output_valid_l = '1') else '0';
    
end Behavioral;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity bl_byte0_85614cf66d is
  port (
    x : in std_logic_vector((32 - 1) downto 0);
    y : out std_logic_vector((8 - 1) downto 0);
    clk : in std_logic;
    ce : in std_logic;
    clr : in std_logic);
end bl_byte0_85614cf66d;
architecture behavior of bl_byte0_85614cf66d is
  signal x_1_22: unsigned((32 - 1) downto 0);
  signal y_2_1_slice: unsigned((8 - 1) downto 0);
begin
  x_1_22 <= std_logic_vector_to_unsigned(x);
  y_2_1_slice <= u2u_slice(x_1_22, 7, 0);
  y <= unsigned_to_std_logic_vector(y_2_1_slice);
end behavior;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity bl_byte1_4dee1560eb is
  port (
    x : in std_logic_vector((32 - 1) downto 0);
    y : out std_logic_vector((8 - 1) downto 0);
    clk : in std_logic;
    ce : in std_logic;
    clr : in std_logic);
end bl_byte1_4dee1560eb;
architecture behavior of bl_byte1_4dee1560eb is
  signal x_1_22: unsigned((32 - 1) downto 0);
  signal y_2_1_slice: unsigned((8 - 1) downto 0);
begin
  x_1_22 <= std_logic_vector_to_unsigned(x);
  y_2_1_slice <= u2u_slice(x_1_22, 15, 8);
  y <= unsigned_to_std_logic_vector(y_2_1_slice);
end behavior;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity bl_byte2_87e71d2c59 is
  port (
    x : in std_logic_vector((32 - 1) downto 0);
    y : out std_logic_vector((8 - 1) downto 0);
    clk : in std_logic;
    ce : in std_logic;
    clr : in std_logic);
end bl_byte2_87e71d2c59;
architecture behavior of bl_byte2_87e71d2c59 is
  signal x_1_22: unsigned((32 - 1) downto 0);
  signal y_2_1_slice: unsigned((8 - 1) downto 0);
begin
  x_1_22 <= std_logic_vector_to_unsigned(x);
  y_2_1_slice <= u2u_slice(x_1_22, 23, 16);
  y <= unsigned_to_std_logic_vector(y_2_1_slice);
end behavior;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity bl_byte3_62ea3ff720 is
  port (
    x : in std_logic_vector((32 - 1) downto 0);
    y : out std_logic_vector((8 - 1) downto 0);
    clk : in std_logic;
    ce : in std_logic;
    clr : in std_logic);
end bl_byte3_62ea3ff720;
architecture behavior of bl_byte3_62ea3ff720 is
  signal x_1_22: unsigned((32 - 1) downto 0);
  signal y_2_1_slice: unsigned((8 - 1) downto 0);
begin
  x_1_22 <= std_logic_vector_to_unsigned(x);
  y_2_1_slice <= u2u_slice(x_1_22, 31, 24);
  y <= unsigned_to_std_logic_vector(y_2_1_slice);
end behavior;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity xldelay is
   generic(width        : integer := -1;
           latency      : integer := -1;
           reg_retiming : integer := 0);
   port(d       : in std_logic_vector (width-1 downto 0);
        ce      : in std_logic;
        clk     : in std_logic;
        en      : in std_logic;
        q       : out std_logic_vector (width-1 downto 0));
end xldelay;
architecture behavior of xldelay is
   component synth_reg
      generic (width       : integer;
               latency     : integer);
      port (i       : in std_logic_vector(width-1 downto 0);
            ce      : in std_logic;
            clr     : in std_logic;
            clk     : in std_logic;
            o       : out std_logic_vector(width-1 downto 0));
   end component;
   component synth_reg_reg
      generic (width       : integer;
               latency     : integer);
      port (i       : in std_logic_vector(width-1 downto 0);
            ce      : in std_logic;
            clr     : in std_logic;
            clk     : in std_logic;
            o       : out std_logic_vector(width-1 downto 0));
   end component;
   signal internal_ce  : std_logic;
begin
   internal_ce  <= ce and en;
   srl_delay: if (reg_retiming = 0) or (latency < 1) generate
     synth_reg_srl_inst : synth_reg
       generic map (
         width   => width,
         latency => latency)
       port map (
         i   => d,
         ce  => internal_ce,
         clr => '0',
         clk => clk,
         o   => q);
   end generate srl_delay;
   reg_delay: if (reg_retiming = 1) and (latency >= 1) generate
     synth_reg_reg_inst : synth_reg_reg
       generic map (
         width   => width,
         latency => latency)
       port map (
         i   => d,
         ce  => internal_ce,
         clr => '0',
         clk => clk,
         o   => q);
   end generate reg_delay;
end architecture behavior;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity lsb1_618afcaae2 is
  port (
    x : in std_logic_vector((32 - 1) downto 0);
    y : out std_logic_vector((30 - 1) downto 0);
    clk : in std_logic;
    ce : in std_logic;
    clr : in std_logic);
end lsb1_618afcaae2;
architecture behavior of lsb1_618afcaae2 is
  signal x_1_22: unsigned((32 - 1) downto 0);
  signal y_2_1_slice: unsigned((30 - 1) downto 0);
begin
  x_1_22 <= std_logic_vector_to_unsigned(x);
  y_2_1_slice <= u2u_slice(x_1_22, 29, 0);
  y <= unsigned_to_std_logic_vector(y_2_1_slice);
end behavior;
----------------------------------------------------------------------------------
-- Company: MRO
-- Engineer: Jan Wagner
-- 
-- Create Date:    13:33:00 12/16/2008
-- Design Name: 
-- Module Name:    rtc32_v14 - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description:
--
--   Maintains RTC time and internal seconds counter.
--   Allows interval trigger signal generation.
--   
--   With a 1PPS input signal present, the RTC time is advanced
--   every time while 1PPS is '1'. An internal seconds count
--   is kept in synch with this 1PPS. Of the external signal
--   has been missing several seconds, the count switches over
--   to the internal seconds counter based on the system clock.
--   
--   The RTC time can be set via time_reload. The new value
--   is loaded on the next 1PPS pulse.
--
--   The SYS_FREQ_HZ should be identical to the frequency
--   of the 'systick' signal.
--
-- Dependencies: 
--
-- Revision: 
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity rtc32_v14 is
    generic (
        SYS_FREQ_HZ : integer := 128000000
    );
    port (
        clk : in std_logic;
        ce  : in std_logic;
        rst : in std_logic;

        -- 1PPS clock signal, x MHz "clock"
        one_pps : in std_logic;
        systick : in std_logic;
    
        -- clock reconfiguration
        time_trigstart : in std_logic_vector(31 downto 0);
        time_trigstop  : in std_logic_vector(31 downto 0);
        time_set       : in std_logic_vector(31 downto 0);
        time_reload    : in std_logic;
        
        -- outputs
        seconds    : out std_logic_vector(31 downto 0) := (others => '0');
        triggered  : out std_logic := '0';
        no_pps     : out std_logic := '0';
        pps_toggle : out std_logic := '0'
  );
end rtc32_v14;

architecture Behavioral of rtc32_v14 is
    
    -- Internal triggering
    signal prev_one_pps       : std_logic := '0';
    signal prev_rtc_step      : std_logic := '0';

    -- delayed inputs
    signal time_trigstart_1 : std_logic_vector(31 downto 0) := (others => '0');
    signal time_trigstop_1  : std_logic_vector(31 downto 0) := (others => '0');
    signal time_set_1       : std_logic_vector(31 downto 0) := (others => '0');
    signal one_pps_1  : std_logic := '0';
    signal systick_1  : std_logic := '0';
    
    -- internals
    signal outseconds   : std_logic_vector(31 downto 0) := (others => '0');
    signal intseconds   : unsigned(31 downto 0) := (others => '0');
    signal extseconds   : unsigned(31 downto 0) := (others => '0');

    signal tickcount_1 : unsigned(31 downto 0) := (others => '0');
    signal longtickcount_1 : unsigned(31 downto 0) := (others => '0');

    signal passed_start   : boolean := false;
    signal passed_start_1 : boolean := false;
    signal before_end     : boolean := false;
    signal before_end_1   : boolean := false;
    
    signal pps_fault : boolean := true;
    
    signal reload_pending  : boolean := false;
    signal reload_done_ext : boolean := false;
    signal reload_done_int : boolean := false;
    
begin

    resample: process(clk)
    begin
    if rising_edge(clk) then
        -- internal
        time_trigstart_1  <= time_trigstart;
        time_trigstop_1   <= time_trigstop;
        time_set_1        <= time_set;
        systick_1         <= systick;
        one_pps_1         <= one_pps;
        if (reload_done_ext or reload_done_int) then
            reload_pending <= false;
        else
            if (time_reload = '1') then
                reload_pending <= true;
            end if;
        end if;
    end if;
    end process;

    outdrive: process(clk)
    begin
    if rising_edge(clk) then
        seconds    <= outseconds;
        pps_toggle <= outseconds(0);
        if (pps_fault) then
            no_pps <= '1';
            outseconds <= std_logic_vector(intseconds);
        else
            no_pps <= '0';
            outseconds <= std_logic_vector(extseconds);
        end if;
    end if;
    end process;

    trigger: process(clk)
    begin
    if rising_edge(clk) then
        passed_start <= (outseconds >= time_trigstart_1);
        before_end   <= (outseconds <= time_trigstop_1);
        passed_start_1 <= passed_start;
        before_end_1   <= before_end;
        if (passed_start_1 and before_end_1) then
            triggered <= '1';
        else
            triggered <= '0';
        end if;
    end if;
    end process;

    -- externally triggered 1PPS
    ext1pps: process(clk, rst)
    begin
    if rising_edge(clk) then
        if (rst = '1') then
            extseconds <= (others=>'0');
            reload_done_ext <= false;
        else            
            if (one_pps_1 = '1') then
                if (reload_pending) then
                    extseconds <= unsigned(time_set_1);
                    reload_done_ext <= true;
                else
                    extseconds <= extseconds + 1;
                    reload_done_ext <= false;
                end if;
            else
                if (pps_fault) then
                    extseconds <= intseconds;
                end if;
            end if;
        end if;
    end if;
    end process;
    
    -- self-generated 1PPS
    int1pps: process(clk, rst)
        variable tickcount_rollover_v : boolean := false; -- for 1*SYS_FREQ_HZ    
        variable tickcount_v : unsigned(31 downto 0) := (others => '0');
    begin
    if rising_edge(clk) then
        if (rst = '1') then
            intseconds <= (others=>'0');
            tickcount_1 <= (others=>'0');
            tickcount_v := (others=>'0');
            tickcount_rollover_v := false;
            reload_done_int <= false;
        else
            if (pps_fault) then
                tickcount_1 <= tickcount_v;
                if (systick_1 = '1') then
                    if (tickcount_rollover_v) then
                        tickcount_v := (others=>'0');
                        if (reload_pending) then
                            intseconds <= unsigned(time_set_1);
                            reload_done_int <= true;
                        else
                            intseconds <= intseconds + 1;
                            reload_done_int <= false;
                        end if;
                    else
                        tickcount_v := tickcount_v + 1;
                    end if;
                end if;
                tickcount_rollover_v := (tickcount_1 = to_unsigned(SYS_FREQ_HZ-2, tickcount_1'length));
            else
                tickcount_v := (others=>'0');
                tickcount_1 <= (others=>'0');
                tickcount_rollover_v := false;
                intseconds <= extseconds;
            end if;
        end if;
    end if;
    end process;
    
    -- external 1PPS fault detection
    faultdetect: process(clk, rst)
        variable longtickcount_rollover_v : boolean := false; -- for 2*SYS_FREQ_HZ
        variable longtickcount_v : unsigned(31 downto 0) := (others => '0');
        variable missed_pps_count_v : integer range 0 to 15;
    begin
    if rising_edge(clk) then
        if (rst = '1') then
            pps_fault <= true;
            longtickcount_1 <= (others=>'0');
            missed_pps_count_v := 0;
            longtickcount_v := (others=>'0');
            longtickcount_rollover_v := false;
        else
            longtickcount_1 <= longtickcount_v;
            if (one_pps_1 = '1') then
                pps_fault <= false;
                longtickcount_v := (others=>'0');
                longtickcount_rollover_v := false;
                missed_pps_count_v := 0;
            else
                if (longtickcount_rollover_v) then
                    longtickcount_v := (others=>'0');
                    if (missed_pps_count_v = 2) then
                        pps_fault <= true;
                    else
                        missed_pps_count_v := missed_pps_count_v + 1;
                    end if;            
                else
                    if (systick_1 = '1') then
                        longtickcount_v := longtickcount_v + 1;
                    end if;
                end if;
                longtickcount_rollover_v := (longtickcount_1 = to_unsigned(2*SYS_FREQ_HZ-2, longtickcount_1'length));
            end if;
        end if;
    end if;
    end process;
         
end Behavioral;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity sl_10lsb_4817575a2c is
  port (
    x : in std_logic_vector((32 - 1) downto 0);
    y : out std_logic_vector((10 - 1) downto 0);
    clk : in std_logic;
    ce : in std_logic;
    clr : in std_logic);
end sl_10lsb_4817575a2c;
architecture behavior of sl_10lsb_4817575a2c is
  signal x_1_22: unsigned((32 - 1) downto 0);
  signal y_2_1_slice: unsigned((10 - 1) downto 0);
begin
  x_1_22 <= std_logic_vector_to_unsigned(x);
  y_2_1_slice <= u2u_slice(x_1_22, 9, 0);
  y <= unsigned_to_std_logic_vector(y_2_1_slice);
end behavior;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity sl_10lsb1_e3e25df95e is
  port (
    x : in std_logic_vector((32 - 1) downto 0);
    y : out std_logic_vector((10 - 1) downto 0);
    clk : in std_logic;
    ce : in std_logic;
    clr : in std_logic);
end sl_10lsb1_e3e25df95e;
architecture behavior of sl_10lsb1_e3e25df95e is
  signal x_1_22: unsigned((32 - 1) downto 0);
  signal y_2_1_slice: unsigned((10 - 1) downto 0);
begin
  x_1_22 <= std_logic_vector_to_unsigned(x);
  y_2_1_slice <= u2u_slice(x_1_22, 9, 0);
  y <= unsigned_to_std_logic_vector(y_2_1_slice);
end behavior;
--
-- (C) 2009 Jan Wagner
--
-- Based on the simpleFIFO example from 
-- http://www.missiontech.co.nz/index.php?page=vhdl
-- which was _not_ a FIFO and not even simple ;-)
--

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity simpleFIFO is
  generic (
    width : integer := 8;
    depth : integer := 10
  );
  port (
    clk   : in std_logic;
    ce    : in std_logic;
    rst   : in std_logic;
    
    wr_en : in std_logic;
    rd_en : in std_logic;
    din   : in std_logic_vector(width-1 downto 0);
    dout  : out std_logic_vector(width-1 downto 0);
    full  : out std_logic;
    empty : out std_logic;
    valid : out std_logic;
    debug : out std_logic_vector(31 downto 0)
  );
end simpleFIFO;

architecture behavioral of simpleFIFO is

  type vector_array is array (0 to depth+1) of std_logic_vector(width-1 downto 0);
  signal memory : vector_array;

begin

  fifo_proc: process(clk, rst)
    variable rd_addr_v  : integer range 0 to depth+1;
    variable wr_addr_v  : integer range 0 to depth+1;
    variable count_v    : integer range 0 to depth+1;
    variable empty_v    : std_logic;
    variable full_v     : std_logic;
  begin

    if rst = '1' then
        full      <= '0';
        empty     <= '1';
        empty_v   := '1';
        full_v    := '0';
        count_v   := 0;
        rd_addr_v := 0;
        wr_addr_v := 0;
    else
        if rising_edge(clk) then
            -- full?
            if count_v = depth then
                full_v := '1';
            else
                full_v := '0';
            end if;
            -- empty?
            if count_v = 0 then
                empty_v := '1';
            else
                empty_v := '0';
            end if;
            -- write to non-full
            if (wr_en = '1' and full_v = '0') then
                memory(wr_addr_v) <= din;
                if wr_addr_v = depth+1 then
                    wr_addr_v := 0;
                else
                    wr_addr_v := wr_addr_v + 1;
                end if;
                count_v := count_v + 1;
            end if;
            -- read from non-empy
            if (rd_en = '1' and empty_v = '0') then
                dout <= memory(rd_addr_v);
                if rd_addr_v = depth + 1 then
                    rd_addr_v := 0;
                else
                    rd_addr_v := rd_addr_v + 1;
                end if;
                count_v := count_v - 1;
                valid <= '1';
            else
                -- data is "valid" only for one cycle after rd_en
                valid <= '0';
            end if;
        end if; -- rising_edge(clk)
    end if; -- async reset
    empty <= empty_v;
    full  <= full_v;
    debug <= std_logic_vector(to_unsigned(count_v, debug'length));
  end process fifo_proc;

end behavioral;
----------------------------------------------------------------------------------
-- Company: MRO
-- Engineer: Jan Wagner
-- License: GNU GPL v3
--
-- Create Date:    12:42:12 12/03/2008
-- Design Name:
-- Module Name:    vdif_packetizer_v15 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:    Packetizes user data into a VDIF style of data frame. The resulting
--                 data frame can be directly forwarded into the 10G UDP packetizer core.
--
--                 The VDIF header is based on the "VDIF Specification Release 1.0" draft.
--
--                 The VDIF Extended User Data field is currently left unused (all 0).
--
--                 The external user IP must take care to align the frame generation
--                 i.e. the first write onto an integer second boundary, if desired.
--                 The Frame# within second VDIF field is maintained inside this vhdl and
--                 is reset to 0 when the Seconds input changes. If the change happens
--                 in the middle of a frame, the frame is nevertheless continued until
--                 the end and the Frame# of the next frame will be 0.
--
--                 When the 'data_in' input rate is slower than the system clock,
--                 the framing works in non-data-replacement mode. If the rates are
--                 the same the first 4 data words are overwritten with the header.
--
-- Dependencies:
--
-- Revision:
-- Additional Comments:
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

--library UNISIM;
--use UNISIM.VComponents.all;

entity vdif_packetizer_v15 is
   generic (
      frameLenLimit : integer := 1024;
      frameCountLimit : integer := 67108864
   );
   port (
      clk : in  std_logic;
      ce  : in  std_logic;
      rst : in  std_logic;

      -- Control
      enable : in std_logic;

      -- User Data input
      data_in    : in std_logic_vector (63 downto 0);
      data_valid : in std_logic;

      -- VDIF Header Field inputs (informative)
      epseconds     : in std_logic_vector (29 downto 0);  -- Seconds from the start of reference epoch
      epoch         : in std_logic_vector (5 downto 0);   -- Epoch# : epoch = 1/1/2000 + (6 months * Epoch#)
      bitspersample : in std_logic_vector (4 downto 0);   -- 0 = 1-bit, ..., 31 = 32-bit
      log2channels  : in std_logic_vector (4 downto 0);   -- 0 = 1 channel, up to 2^5=32 channels
      complex       : in std_logic; -- 1 if payload consists of complex data samples
      thread_id     : in std_logic_vector (9 downto 0);   -- thread ID from 0 to 1023
      station_id    : in std_logic_vector (15 downto 0);  -- 2-character station ID like 'Mh' or 'Jv'
      dw64_per_frame: in std_logic_vector (9 downto 0);   -- how many doublewords including the header

-- debug out
      dbg_dw64counter: out std_logic_vector (9 downto 0);
      dbg_fifo_empty: out std_logic;

      -- Output to 10G UDP packetizer
      tx_data         : out std_logic_vector (63 downto 0) := (others=>'0');
      tx_valid        : out std_logic := '0';
      tx_end_of_frame : out std_logic := '0';
      tx_discard      : out std_logic := '0'
   );
end vdif_packetizer_v15;

architecture Behavioral of vdif_packetizer_v15 is

   component simpleFIFO is
      generic (
         width : integer := 64;
         depth : integer := 8
      );
      port (
         clk   : in  std_logic;
         ce    : in  std_logic;
         rst   : in  std_logic;
         wr_en : in std_logic;
         rd_en : in std_logic;
         din   : in  std_logic_vector(width-1 downto 0);
         dout  : out std_logic_vector(width-1 downto 0);
         full  : out std_logic;
         empty : out std_logic;
         valid : out std_logic;
         debug : out std_logic_vector(31 downto 0)
      );
   end component;
   constant width : integer := 64;
   constant depth : integer := 10;

   signal datafifo_rden  :   std_logic := '0';
   signal datafifo_empty :   std_logic := '0';
   signal datafifo_valid :   std_logic := '0';
   signal datafifo_dout  :   std_logic_vector (63 downto 0);

   -- Constants
   constant HEADER_DW_LENGTH: integer := 4; -- VDIF Header length in doublewords
   type vdif_fsm_state is (
      WAIT_DATA,
      SEND_HDR_DWORD0,
      SEND_HDR_DWORD1,
      SEND_HDR_DWORD2,
      SEND_HDR_DWORD3,
      SEND_USERDATA
   );

   signal vdif_state : vdif_fsm_state := WAIT_DATA;

   signal dw64_count_prefinal : std_logic; -- '1' when one value short of a full frame
   signal dw64_count_ended : std_logic;
   signal clockin_enable   : std_logic;

   -- VDIF data frame# within current second
   signal frame_nr     : std_logic_vector(23 downto 0) := (others=>'0');

   -- 1PPS recovery from RTC / epoch seconds
   signal pps_pulse        : std_logic := '0';
   
   -- resampled inputs
   signal s_dw64_per_frame : std_logic_vector (9 downto 0) := (0=>'1', others=>'0');
   signal s_dw64_per_frame_m1 : std_logic_vector (9 downto 0) := (others=>'0');
   signal s_bitspersample_m1 : std_logic_vector (4 downto 0) := (others=>'0');
   signal s_epseconds : std_logic_vector (29 downto 0) := (others=>'0');
   signal s_epoch : std_logic_vector (5 downto 0) := (others=>'0');
   
begin

   -- User input port via FIFO
   datainput_fifo: simpleFIFO
   generic map (
      width => width,
      depth => depth)
   port map (
      clk   => clk,
      ce    => '1',
      rst   => rst,
      din   => data_in,
      wr_en => data_valid,
      rd_en => datafifo_rden,
      dout  => datafifo_dout,
      empty => datafifo_empty,
      full  => open,
      valid => datafifo_valid,
      debug => open
   );

   -- other resampled signals
   resample: process(clk)
   begin
       if clk'event and clk = '1' then
          s_epoch <= epoch;
          s_epseconds <= epseconds;
          s_dw64_per_frame <= dw64_per_frame;
          s_dw64_per_frame_m1 <= std_logic_vector(unsigned(dw64_per_frame) - 1);
          s_bitspersample_m1 <= std_logic_vector(unsigned(bitspersample) - 1);
       end if;
   end process;
   
   dbg_fifo_empty <= datafifo_empty;
   
   -- put something onto the 10G
   with vdif_state select tx_data <=
      -- no data
      (others => '0') when WAIT_DATA,
      -- Header dw#0: Invalid, Legacy, Epoch Secs | 2 unassigned, Ref Epoch, Frame# within second
      ('0' & '0' & s_epseconds & "00" & s_epoch & frame_nr) when SEND_HDR_DWORD0,
      -- Header dw#1: Version, log2channels, data frame len in 64-bit words minus 1|
      --              C1 real/complex, bitspersample minus 1, threadID, station ID
      ("000" & log2channels & "00000000000000" & s_dw64_per_frame_m1 
       & '0' & s_bitspersample_m1 & thread_id & station_id) when SEND_HDR_DWORD1,
      -- Header dw#2: Extended Data Version (0=unused), Extended user data 1+2
      (others=>'0') when SEND_HDR_DWORD2,
      -- Header dw#3: Extendend User Data
      (others=>'0') when SEND_HDR_DWORD3,
      -- VDIF Payload
      datafifo_dout when SEND_USERDATA,
      -- illegal state
      (others => '1') when others;

   with vdif_state select tx_valid <=
      '0' when WAIT_DATA,
      '1' when SEND_HDR_DWORD0,
      '1' when SEND_HDR_DWORD1,
      '1' when SEND_HDR_DWORD2,
      '1' when SEND_HDR_DWORD3,
      datafifo_valid when SEND_USERDATA,
      '0' when others;

   with vdif_state select tx_end_of_frame <=
      (dw64_count_prefinal and datafifo_valid) when SEND_USERDATA,
      '0' when others;

   -- State machine for creating VDIF frames
   frame_fsm_proc: process(clk, rst)
   begin
      if (rst = '1') then
         clockin_enable <= '0';
         tx_discard     <= '1';
         vdif_state     <= WAIT_DATA;
      else
         if rising_edge(clk) then
            -- FSM
            case vdif_state is
               when WAIT_DATA =>
                  tx_discard <= '0';
                  if datafifo_empty = '1' then
                     vdif_state <= WAIT_DATA;
                  else
                     vdif_state <= SEND_HDR_DWORD0;
                  end if;
               when SEND_HDR_DWORD0 =>
                  vdif_state <= SEND_HDR_DWORD1;
               when SEND_HDR_DWORD1 =>
                  vdif_state <= SEND_HDR_DWORD2;
               when SEND_HDR_DWORD2 =>
                  vdif_state <= SEND_HDR_DWORD3;
                  clockin_enable <= '1'; -- set 2 clks early due to latency of FIFO
               when SEND_HDR_DWORD3 =>
                  -- clockin_enable <= '1'; -- set early due to latency of FIFO
                  vdif_state <= SEND_USERDATA;
               when SEND_USERDATA =>
                  if dw64_count_ended = '1' then
                     clockin_enable <= '0';
                     --if datafifo_empty = '1' then
                        vdif_state <= WAIT_DATA;
                     --else
                     --   vdif_state <= SEND_HDR_DWORD0;
                     --end if;
                  else
                     clockin_enable <= '1';
                     vdif_state <= SEND_USERDATA;
                  end if;
               when others =>
                  vdif_state <= WAIT_DATA;
            end case;
         end if;
      end if;
   end process frame_fsm_proc;

   -- Frame counter: is reset to 0 when second changes, 
   --                and is incremented after current VDIF header sent
   frame_counter_proc: process(clk, rst)
      variable framecounter_v : integer range 0 to frameCountLimit;
      variable old_epsecond_v : std_logic;
      variable seconds_changed_v : std_logic;
   begin
      if (rst = '1') then
         framecounter_v := 0;
         old_epsecond_v := epseconds(0); -- not using s_epseconds() here
         seconds_changed_v := '0';
      else
         if rising_edge(clk) then
             -- during frame
             if (epseconds(0) /= old_epsecond_v) then
                seconds_changed_v := '1';
             end if;
             old_epsecond_v := epseconds(0);             
             -- immediately before start of next frame
             if (vdif_state = WAIT_DATA and datafifo_empty = '0') then
                if (seconds_changed_v = '1') then
                    framecounter_v := 0;
                else
                    framecounter_v := framecounter_v + 1;
                end if;
                seconds_changed_v := '0';               
             end if;
          end if;
      end if;
      frame_nr <= std_logic_vector(to_unsigned(framecounter_v, frame_nr'length));
      dbg_dw64counter <= std_logic_vector(to_unsigned(framecounter_v, dbg_dw64counter'length));
   end process frame_counter_proc;

   -- Clock out a number of doublewords into 'vdif_userdata'
   frame_doubleword_proc: process(clk, rst)
      variable dw64_target_v          : integer range 0 to frameLenLimit;
      variable dw64_target_minus1_v   : integer range 0 to frameLenLimit;
      variable dw64_count_v           : integer range 0 to frameLenLimit;
      variable dw64_count_plus1_v     : integer range 0 to frameLenLimit;
      variable dw64_count_prefinal_v  : std_logic;
      variable dw64_count_done_v      : std_logic;
   begin
      if rst = '1' then
         dw64_target_v := 256;
         dw64_count_v  := HEADER_DW_LENGTH;
         dw64_target_minus1_v  := 256 - 1;
         dw64_count_plus1_v    := HEADER_DW_LENGTH + 1;
         dw64_count_prefinal_v := '0';
         dw64_count_done_v     := '0';
         datafifo_rden <= '0';
         dw64_count_prefinal <= '0';
         dw64_count_ended    <= '0';
   else
         if rising_edge(clk) then
            if (clockin_enable = '1') then
               -- get more data from FIFO
               datafifo_rden <= not datafifo_empty;
               if (datafifo_valid = '1') then
                  dw64_count_v := dw64_count_plus1_v;   -- dw64_count_v + 1;
               end if;
               -- one value short of a full frame?
               if (dw64_count_v = dw64_target_minus1_v) then
                  dw64_count_prefinal_v := '1';
               end if;
               -- full frame done?
               if (dw64_count_v = dw64_target_v) then
                  dw64_count_done_v := '1';
               else
                  dw64_count_done_v := '0';
               end if;
            else
               -- not assembling a frame, pre-load the configuration
               datafifo_rden <= '0';
               dw64_count_v  := HEADER_DW_LENGTH;
               dw64_target_v := to_integer(unsigned(s_dw64_per_frame));
               dw64_count_prefinal_v := '0';
               dw64_count_done_v     := '0';
            end if; -- clockin_enable
            dw64_target_minus1_v := dw64_target_v - 1;
            dw64_count_plus1_v   := dw64_count_v + 1;
            dw64_count_prefinal <= dw64_count_prefinal_v;
            dw64_count_ended    <= dw64_count_done_v;
            -- dbg_dw64counter  <= std_logic_vector(to_unsigned(dw64_count_v, dbg_dw64counter'length));
         end if; -- clk
      end if; -- rst
   end process frame_doubleword_proc;

end Behavioral;

-------------------------------------------------------------------
-- System Generator version 9.1.01 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices.  By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement.  You are responsible for obtaining any rights
-- you may require for your implementation.  Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems.  Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity xlregister is
   generic (d_width          : integer := 5;
            init_value       : bit_vector := b"00");
   port (d   : in std_logic_vector (d_width-1 downto 0);
         rst : in std_logic_vector(0 downto 0) := "0";
         en  : in std_logic_vector(0 downto 0) := "1";
         ce  : in std_logic;
         clk : in std_logic;
         q   : out std_logic_vector (d_width-1 downto 0));
end xlregister;
architecture behavior of xlregister is
   component synth_reg_w_init
      generic (width      : integer;
               init_index : integer;
               init_value : bit_vector;
               latency    : integer);
      port (i   : in std_logic_vector(width-1 downto 0);
            ce  : in std_logic;
            clr : in std_logic;
            clk : in std_logic;
            o   : out std_logic_vector(width-1 downto 0));
   end component;
   -- synopsys translate_off
   signal real_d, real_q           : real;
   -- synopsys translate_on
   signal internal_clr             : std_logic;
   signal internal_ce              : std_logic;
begin
   internal_clr <= rst(0) and ce;
   internal_ce  <= en(0) and ce;
   synth_reg_inst : synth_reg_w_init
      generic map (width      => d_width,
                   init_index => 2,
                   init_value => init_value,
                   latency    => 1)
      port map (i   => d,
                ce  => internal_ce,
                clr => internal_clr,
                clk => clk,
                o   => q);
end architecture behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;

-- Generated from Simulink block "expres4g1024M/ADCCat1"

entity adccat1_entity_e02ada5f8a is
  port (
    iq0: in std_logic_vector(7 downto 0);
    iq1: in std_logic_vector(7 downto 0);
    iq2: in std_logic_vector(7 downto 0);
    iq3: in std_logic_vector(7 downto 0);
    cat: out std_logic_vector(31 downto 0)
  );
end adccat1_entity_e02ada5f8a;

architecture structural of adccat1_entity_e02ada5f8a is
  signal concat1_y_net_x0: std_logic_vector(31 downto 0);
  signal reinterpret1_output_port_net: std_logic_vector(7 downto 0);
  signal reinterpret2_output_port_net: std_logic_vector(7 downto 0);
  signal reinterpret3_output_port_net: std_logic_vector(7 downto 0);
  signal reinterpret4_output_port_net: std_logic_vector(7 downto 0);
  signal reinterpret_output_port_net_x3: std_logic_vector(7 downto 0);
  signal reinterpret_output_port_net_x4: std_logic_vector(7 downto 0);
  signal reinterpret_output_port_net_x5: std_logic_vector(7 downto 0);
  signal reinterpret_output_port_net_x6: std_logic_vector(7 downto 0);

begin
  reinterpret_output_port_net_x3 <= iq0;
  reinterpret_output_port_net_x4 <= iq1;
  reinterpret_output_port_net_x5 <= iq2;
  reinterpret_output_port_net_x6 <= iq3;
  cat <= concat1_y_net_x0;

  concat1: entity work.concat1_91f6e5894e
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      in0 => reinterpret3_output_port_net,
      in1 => reinterpret2_output_port_net,
      in2 => reinterpret4_output_port_net,
      in3 => reinterpret1_output_port_net,
      y => concat1_y_net_x0
    );

  reinterpret1: entity work.reinterpret1_421868fdcf
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      input_port => reinterpret_output_port_net_x6,
      output_port => reinterpret1_output_port_net
    );

  reinterpret2: entity work.reinterpret2_af838af55d
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      input_port => reinterpret_output_port_net_x4,
      output_port => reinterpret2_output_port_net
    );

  reinterpret3: entity work.reinterpret3_8118b8df3f
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      input_port => reinterpret_output_port_net_x3,
      output_port => reinterpret3_output_port_net
    );

  reinterpret4: entity work.reinterpret4_b77a7b0ce0
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      input_port => reinterpret_output_port_net_x5,
      output_port => reinterpret4_output_port_net
    );

end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;

-- Generated from Simulink block "expres4g1024M/ADCCat2"

entity adccat2_entity_ceac40d612 is
  port (
    iq0: in std_logic_vector(7 downto 0);
    iq1: in std_logic_vector(7 downto 0);
    iq2: in std_logic_vector(7 downto 0);
    iq3: in std_logic_vector(7 downto 0);
    cat: out std_logic_vector(31 downto 0)
  );
end adccat2_entity_ceac40d612;

architecture structural of adccat2_entity_ceac40d612 is
  signal concat1_y_net_x0: std_logic_vector(31 downto 0);
  signal reinterpret1_output_port_net: std_logic_vector(7 downto 0);
  signal reinterpret2_output_port_net: std_logic_vector(7 downto 0);
  signal reinterpret3_output_port_net: std_logic_vector(7 downto 0);
  signal reinterpret4_output_port_net: std_logic_vector(7 downto 0);
  signal reinterpret_output_port_net_x3: std_logic_vector(7 downto 0);
  signal reinterpret_output_port_net_x4: std_logic_vector(7 downto 0);
  signal reinterpret_output_port_net_x5: std_logic_vector(7 downto 0);
  signal reinterpret_output_port_net_x6: std_logic_vector(7 downto 0);

begin
  reinterpret_output_port_net_x3 <= iq0;
  reinterpret_output_port_net_x4 <= iq1;
  reinterpret_output_port_net_x5 <= iq2;
  reinterpret_output_port_net_x6 <= iq3;
  cat <= concat1_y_net_x0;

  concat1: entity work.concat1_8254fe26d1
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      in0 => reinterpret3_output_port_net,
      in1 => reinterpret2_output_port_net,
      in2 => reinterpret4_output_port_net,
      in3 => reinterpret1_output_port_net,
      y => concat1_y_net_x0
    );

  reinterpret1: entity work.reinterpret1_209a7f1ccf
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      input_port => reinterpret_output_port_net_x6,
      output_port => reinterpret1_output_port_net
    );

  reinterpret2: entity work.reinterpret2_f735414ec3
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      input_port => reinterpret_output_port_net_x4,
      output_port => reinterpret2_output_port_net
    );

  reinterpret3: entity work.reinterpret3_f487f886c1
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      input_port => reinterpret_output_port_net_x3,
      output_port => reinterpret3_output_port_net
    );

  reinterpret4: entity work.reinterpret4_5b4e0dc295
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      input_port => reinterpret_output_port_net_x5,
      output_port => reinterpret4_output_port_net
    );

end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;

-- Generated from Simulink block "expres4g1024M/ADCunCat1"

entity adcuncat1_entity_eb19c49dca is
  port (
    concat: in std_logic_vector(31 downto 0);
    iq0: out std_logic_vector(7 downto 0);
    iq1: out std_logic_vector(7 downto 0);
    iq2: out std_logic_vector(7 downto 0);
    iq3: out std_logic_vector(7 downto 0)
  );
end adcuncat1_entity_eb19c49dca;

architecture structural of adcuncat1_entity_eb19c49dca is
  signal bit0_y_net: std_logic_vector(7 downto 0);
  signal bit16_y_net: std_logic_vector(7 downto 0);
  signal bit24_y_net: std_logic_vector(7 downto 0);
  signal bit8_y_net: std_logic_vector(7 downto 0);
  signal concat1_y_net_x1: std_logic_vector(31 downto 0);
  signal reinterpret4_output_port_net_x0: std_logic_vector(7 downto 0);
  signal reinterpret5_output_port_net_x0: std_logic_vector(7 downto 0);
  signal reinterpret6_output_port_net_x0: std_logic_vector(7 downto 0);
  signal reinterpret7_output_port_net_x0: std_logic_vector(7 downto 0);

begin
  concat1_y_net_x1 <= concat;
  iq0 <= reinterpret4_output_port_net_x0;
  iq1 <= reinterpret5_output_port_net_x0;
  iq2 <= reinterpret6_output_port_net_x0;
  iq3 <= reinterpret7_output_port_net_x0;

  bit0: entity work.bit0_eab550d1c0
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      x => concat1_y_net_x1,
      y => bit0_y_net
    );

  bit16: entity work.bit16_f5ebc38801
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      x => concat1_y_net_x1,
      y => bit16_y_net
    );

  bit24: entity work.bit24_c653e87f15
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      x => concat1_y_net_x1,
      y => bit24_y_net
    );

  bit8: entity work.bit8_6a4da2d14b
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      x => concat1_y_net_x1,
      y => bit8_y_net
    );

  reinterpret4: entity work.reinterpret4_2cede6fcef
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      input_port => bit24_y_net,
      output_port => reinterpret4_output_port_net_x0
    );

  reinterpret5: entity work.reinterpret5_ddc5355546
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      input_port => bit16_y_net,
      output_port => reinterpret5_output_port_net_x0
    );

  reinterpret6: entity work.reinterpret6_0562bbbdfa
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      input_port => bit8_y_net,
      output_port => reinterpret6_output_port_net_x0
    );

  reinterpret7: entity work.reinterpret7_28693a4e8c
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      input_port => bit0_y_net,
      output_port => reinterpret7_output_port_net_x0
    );

end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;

-- Generated from Simulink block "expres4g1024M/ADCunCat2"

entity adcuncat2_entity_4514881654 is
  port (
    concat: in std_logic_vector(31 downto 0);
    iq0: out std_logic_vector(7 downto 0);
    iq1: out std_logic_vector(7 downto 0);
    iq2: out std_logic_vector(7 downto 0);
    iq3: out std_logic_vector(7 downto 0)
  );
end adcuncat2_entity_4514881654;

architecture structural of adcuncat2_entity_4514881654 is
  signal bit0_y_net: std_logic_vector(7 downto 0);
  signal bit16_y_net: std_logic_vector(7 downto 0);
  signal bit24_y_net: std_logic_vector(7 downto 0);
  signal bit8_y_net: std_logic_vector(7 downto 0);
  signal concat1_y_net_x1: std_logic_vector(31 downto 0);
  signal reinterpret4_output_port_net_x0: std_logic_vector(7 downto 0);
  signal reinterpret5_output_port_net_x0: std_logic_vector(7 downto 0);
  signal reinterpret6_output_port_net_x0: std_logic_vector(7 downto 0);
  signal reinterpret7_output_port_net_x0: std_logic_vector(7 downto 0);

begin
  concat1_y_net_x1 <= concat;
  iq0 <= reinterpret4_output_port_net_x0;
  iq1 <= reinterpret5_output_port_net_x0;
  iq2 <= reinterpret6_output_port_net_x0;
  iq3 <= reinterpret7_output_port_net_x0;

  bit0: entity work.bit0_5b70faa9e1
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      x => concat1_y_net_x1,
      y => bit0_y_net
    );

  bit16: entity work.bit16_0899a8c2cd
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      x => concat1_y_net_x1,
      y => bit16_y_net
    );

  bit24: entity work.bit24_6703f73bb4
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      x => concat1_y_net_x1,
      y => bit24_y_net
    );

  bit8: entity work.bit8_a5f685fcb4
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      x => concat1_y_net_x1,
      y => bit8_y_net
    );

  reinterpret4: entity work.reinterpret4_0bfe5a8dd8
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      input_port => bit24_y_net,
      output_port => reinterpret4_output_port_net_x0
    );

  reinterpret5: entity work.reinterpret5_ad5fcc0cc6
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      input_port => bit16_y_net,
      output_port => reinterpret5_output_port_net_x0
    );

  reinterpret6: entity work.reinterpret6_0f88bc95f6
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      input_port => bit8_y_net,
      output_port => reinterpret6_output_port_net_x0
    );

  reinterpret7: entity work.reinterpret7_1f25723006
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      input_port => bit0_y_net,
      output_port => reinterpret7_output_port_net_x0
    );

end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;

-- Generated from Simulink block "expres4g1024M/AssembleStatus"

entity assemblestatus_entity_7fd680fdc6 is
  port (
    adcvalid: in std_logic;
    onepps: in std_logic;
    oneppsfault: in std_logic;
    rtctoggled: in std_logic;
    rtctriggered: in std_logic;
    status: out std_logic_vector(91 downto 0)
  );
end assemblestatus_entity_7fd680fdc6;

architecture structural of assemblestatus_entity_7fd680fdc6 is
  signal concat1_y_net_x0: std_logic_vector(91 downto 0);
  signal concat2_y_net: std_logic_vector(75 downto 0);
  signal concat3_y_net: std_logic_vector(7 downto 0);
  signal concat_y_net: std_logic_vector(67 downto 0);
  signal constant1_op_net: std_logic_vector(15 downto 0);
  signal constant2_op_net: std_logic;
  signal constant3_op_net: std_logic_vector(15 downto 0);
  signal constant4_op_net: std_logic_vector(15 downto 0);
  signal constant5_op_net: std_logic_vector(15 downto 0);
  signal constant6_op_net: std_logic_vector(15 downto 0);
  signal expres4g1024m_adc_user_data_valid_net_x0: std_logic;
  signal logical1_y_net_x0: std_logic;
  signal rtc32_v14_no_pps_net_x0: std_logic;
  signal rtc32_v14_pps_toggle_net_x0: std_logic;
  signal rtc32_v14_triggered_net_x0: std_logic;

begin
  expres4g1024m_adc_user_data_valid_net_x0 <= adcvalid;
  logical1_y_net_x0 <= onepps;
  rtc32_v14_no_pps_net_x0 <= oneppsfault;
  rtc32_v14_pps_toggle_net_x0 <= rtctoggled;
  rtc32_v14_triggered_net_x0 <= rtctriggered;
  status <= concat1_y_net_x0;

  concat: entity work.concat_d694665e71
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      in0 => constant3_op_net,
      in1 => constant4_op_net,
      in2(0) => expres4g1024m_adc_user_data_valid_net_x0,
      in3(0) => rtc32_v14_pps_toggle_net_x0,
      in4(0) => logical1_y_net_x0,
      in5 => constant5_op_net,
      in6 => constant6_op_net,
      in7(0) => rtc32_v14_triggered_net_x0,
      y => concat_y_net
    );

  concat1: entity work.concat1_3055210e70
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      in0 => constant1_op_net,
      in1 => concat2_y_net,
      y => concat1_y_net_x0
    );

  concat2: entity work.concat2_7c7ec05f81
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      in0 => concat3_y_net,
      in1 => concat_y_net,
      y => concat2_y_net
    );

  concat3: entity work.concat3_c4dc34b1a7
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      in0(0) => constant2_op_net,
      in1(0) => constant2_op_net,
      in2(0) => constant2_op_net,
      in3(0) => constant2_op_net,
      in4(0) => constant2_op_net,
      in5(0) => constant2_op_net,
      in6(0) => constant2_op_net,
      in7(0) => rtc32_v14_no_pps_net_x0,
      y => concat3_y_net
    );

  constant1: entity work.constant1_699d7f1eeb
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      op => constant1_op_net
    );

  constant2: entity work.constant2_5f1cd7b048
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      op(0) => constant2_op_net
    );

  constant3: entity work.constant3_d786e11d4e
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      op => constant3_op_net
    );

  constant4: entity work.constant4_21438855e4
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      op => constant4_op_net
    );

  constant5: entity work.constant5_075adb46bf
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      op => constant5_op_net
    );

  constant6: entity work.constant6_49c14364ee
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      op => constant6_op_net
    );

end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;

-- Generated from Simulink block "expres4g1024M/ConfigSys"

entity configsys_entity_72b77062d8 is
  port (
    configreg: in std_logic_vector(31 downto 0);
    bitspersample: out std_logic_vector(4 downto 0);
    log2channels: out std_logic_vector(4 downto 0);
    reloadrtc: out std_logic;
    stationid: out std_logic_vector(15 downto 0);
    sysreset: out std_logic
  );
end configsys_entity_72b77062d8;

architecture structural of configsys_entity_72b77062d8 is
  signal concat_y_net: std_logic_vector(15 downto 0);
  signal constant8_op_net: std_logic_vector(7 downto 0);
  signal dly6_q_net_x0: std_logic_vector(31 downto 0);
  signal lsb1_y_net: std_logic;
  signal lsb3_y_net: std_logic;
  signal simulation_multiplexer2_dout_net_x0: std_logic;
  signal simulation_multiplexer3_dout_net_x0: std_logic_vector(15 downto 0);
  signal simulation_multiplexer4_dout_net_x0: std_logic_vector(4 downto 0);
  signal simulation_multiplexer5_dout_net_x0: std_logic_vector(4 downto 0);
  signal simulation_multiplexer_dout_net_x0: std_logic;
  signal sl_5lsb_1_y_net: std_logic_vector(4 downto 0);
  signal sl_5lsb_y_net: std_logic_vector(4 downto 0);
  signal sl_byte0_y_net: std_logic_vector(7 downto 0);
  signal sl_byte1_y_net: std_logic_vector(7 downto 0);
  signal sl_byte2_y_net: std_logic_vector(7 downto 0);
  signal sl_byte3_y_net: std_logic_vector(7 downto 0);

begin
  dly6_q_net_x0 <= configreg;
  bitspersample <= simulation_multiplexer4_dout_net_x0;
  log2channels <= simulation_multiplexer5_dout_net_x0;
  reloadrtc <= simulation_multiplexer_dout_net_x0;
  stationid <= simulation_multiplexer3_dout_net_x0;
  sysreset <= simulation_multiplexer2_dout_net_x0;

  concat: entity work.concat_df7186a2e1
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      in0 => sl_byte2_y_net,
      in1 => sl_byte1_y_net,
      y => concat_y_net
    );

  constant8: entity work.constant8_cb133a1117
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      op => constant8_op_net
    );

  lsb1: entity work.lsb1_e6a95c1af1
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      x => sl_byte0_y_net,
      y(0) => lsb1_y_net
    );

  lsb3: entity work.lsb3_b3a1c0e2cd
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      x => sl_byte0_y_net,
      y(0) => lsb3_y_net
    );

  simulation_multiplexer: entity work.xlpassthrough
    generic map (
      din_width => 1,
      dout_width => 1
    )
    port map (
      din(0) => lsb1_y_net,
      dout(0) => simulation_multiplexer_dout_net_x0
    );

  simulation_multiplexer2: entity work.xlpassthrough
    generic map (
      din_width => 1,
      dout_width => 1
    )
    port map (
      din(0) => lsb3_y_net,
      dout(0) => simulation_multiplexer2_dout_net_x0
    );

  simulation_multiplexer3: entity work.xlpassthrough
    generic map (
      din_width => 16,
      dout_width => 16
    )
    port map (
      din => concat_y_net,
      dout => simulation_multiplexer3_dout_net_x0
    );

  simulation_multiplexer4: entity work.xlpassthrough
    generic map (
      din_width => 5,
      dout_width => 5
    )
    port map (
      din => sl_5lsb_y_net,
      dout => simulation_multiplexer4_dout_net_x0
    );

  simulation_multiplexer5: entity work.xlpassthrough
    generic map (
      din_width => 5,
      dout_width => 5
    )
    port map (
      din => sl_5lsb_1_y_net,
      dout => simulation_multiplexer5_dout_net_x0
    );

  sl_5lsb: entity work.sl_5lsb_82c15f848e
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      x => sl_byte3_y_net,
      y => sl_5lsb_y_net
    );

  sl_5lsb_1: entity work.sl_5lsb_1_85931bdd03
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      x => constant8_op_net,
      y => sl_5lsb_1_y_net
    );

  sl_byte0: entity work.sl_byte0_4d9050d309
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      x => dly6_q_net_x0,
      y => sl_byte0_y_net
    );

  sl_byte1: entity work.sl_byte1_21a54b9e61
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      x => dly6_q_net_x0,
      y => sl_byte1_y_net
    );

  sl_byte2: entity work.sl_byte2_3628a88f76
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      x => dly6_q_net_x0,
      y => sl_byte2_y_net
    );

  sl_byte3: entity work.sl_byte3_9d1210cfbd
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      x => dly6_q_net_x0,
      y => sl_byte3_y_net
    );

end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;

-- Generated from Simulink block "expres4g1024M/PosEdge"

entity posedge_entity_aac04e502a is
  port (
    ce_1: in std_logic;
    clk_1: in std_logic;
    in1: in std_logic;
    out1: out std_logic
  );
end posedge_entity_aac04e502a;

architecture structural of posedge_entity_aac04e502a is
  signal ce_1_sg_x0: std_logic;
  signal clk_1_sg_x0: std_logic;
  signal inverter2_op_net: std_logic;
  signal logical1_y_net_x1: std_logic;
  signal logical_y_net_x0: std_logic;

begin
  ce_1_sg_x0 <= ce_1;
  clk_1_sg_x0 <= clk_1;
  logical_y_net_x0 <= in1;
  out1 <= logical1_y_net_x1;

  inverter2: entity work.inverter2_2ab0852d89
    port map (
      ce => ce_1_sg_x0,
      clk => clk_1_sg_x0,
      clr => '0',
      ip(0) => logical_y_net_x0,
      op(0) => inverter2_op_net
    );

  logical1: entity work.logical1_dc01bcb7e5
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      d0(0) => inverter2_op_net,
      d1(0) => logical_y_net_x0,
      y(0) => logical1_y_net_x1
    );

end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;

-- Generated from Simulink block "expres4g1024M/adc/conv"

entity conv_entity_f5df0b0e65 is
  port (
    ce_1: in std_logic;
    clk_1: in std_logic;
    in1: in std_logic_vector(7 downto 0);
    out1: out std_logic_vector(7 downto 0)
  );
end conv_entity_f5df0b0e65;

architecture structural of conv_entity_f5df0b0e65 is
  signal ce_1_sg_x1: std_logic;
  signal clk_1_sg_x1: std_logic;
  signal concat_y_net: std_logic_vector(7 downto 0);
  signal expres4g1024m_adc_user_datai0_net_x0: std_logic_vector(7 downto 0);
  signal inverter_op_net: std_logic;
  signal reinterpret_output_port_net_x4: std_logic_vector(7 downto 0);
  signal slice1_y_net: std_logic_vector(6 downto 0);
  signal slice_y_net: std_logic;

begin
  ce_1_sg_x1 <= ce_1;
  clk_1_sg_x1 <= clk_1;
  expres4g1024m_adc_user_datai0_net_x0 <= in1;
  out1 <= reinterpret_output_port_net_x4;

  concat: entity work.concat_bc5e36d4ea
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      in0(0) => inverter_op_net,
      in1 => slice1_y_net,
      y => concat_y_net
    );

  inverter: entity work.inverter_e88d30344f
    port map (
      ce => ce_1_sg_x1,
      clk => clk_1_sg_x1,
      clr => '0',
      ip(0) => slice_y_net,
      op(0) => inverter_op_net
    );

  reinterpret: entity work.reinterpret_bb5704daa0
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      input_port => concat_y_net,
      output_port => reinterpret_output_port_net_x4
    );

  slice: entity work.slice_ada6dabeed
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      x => expres4g1024m_adc_user_datai0_net_x0,
      y(0) => slice_y_net
    );

  slice1: entity work.slice1_024135aade
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      x => expres4g1024m_adc_user_datai0_net_x0,
      y => slice1_y_net
    );

end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;

-- Generated from Simulink block "expres4g1024M/adc/conv1"

entity conv1_entity_99e0255406 is
  port (
    ce_1: in std_logic;
    clk_1: in std_logic;
    in1: in std_logic_vector(7 downto 0);
    out1: out std_logic_vector(7 downto 0)
  );
end conv1_entity_99e0255406;

architecture structural of conv1_entity_99e0255406 is
  signal ce_1_sg_x2: std_logic;
  signal clk_1_sg_x2: std_logic;
  signal concat_y_net: std_logic_vector(7 downto 0);
  signal expres4g1024m_adc_user_datai1_net_x0: std_logic_vector(7 downto 0);
  signal inverter_op_net: std_logic;
  signal reinterpret_output_port_net_x5: std_logic_vector(7 downto 0);
  signal slice1_y_net: std_logic_vector(6 downto 0);
  signal slice_y_net: std_logic;

begin
  ce_1_sg_x2 <= ce_1;
  clk_1_sg_x2 <= clk_1;
  expres4g1024m_adc_user_datai1_net_x0 <= in1;
  out1 <= reinterpret_output_port_net_x5;

  concat: entity work.concat_ddc54e5835
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      in0(0) => inverter_op_net,
      in1 => slice1_y_net,
      y => concat_y_net
    );

  inverter: entity work.inverter_b526fbe439
    port map (
      ce => ce_1_sg_x2,
      clk => clk_1_sg_x2,
      clr => '0',
      ip(0) => slice_y_net,
      op(0) => inverter_op_net
    );

  reinterpret: entity work.reinterpret_d4aaa1bdfb
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      input_port => concat_y_net,
      output_port => reinterpret_output_port_net_x5
    );

  slice: entity work.slice_548b816da1
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      x => expres4g1024m_adc_user_datai1_net_x0,
      y(0) => slice_y_net
    );

  slice1: entity work.slice1_ca2b52d742
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      x => expres4g1024m_adc_user_datai1_net_x0,
      y => slice1_y_net
    );

end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;

-- Generated from Simulink block "expres4g1024M/adc/conv2"

entity conv2_entity_8ea5768454 is
  port (
    ce_1: in std_logic;
    clk_1: in std_logic;
    in1: in std_logic_vector(7 downto 0);
    out1: out std_logic_vector(7 downto 0)
  );
end conv2_entity_8ea5768454;

architecture structural of conv2_entity_8ea5768454 is
  signal ce_1_sg_x3: std_logic;
  signal clk_1_sg_x3: std_logic;
  signal concat_y_net: std_logic_vector(7 downto 0);
  signal expres4g1024m_adc_user_datai2_net_x0: std_logic_vector(7 downto 0);
  signal inverter_op_net: std_logic;
  signal reinterpret_output_port_net_x6: std_logic_vector(7 downto 0);
  signal slice1_y_net: std_logic_vector(6 downto 0);
  signal slice_y_net: std_logic;

begin
  ce_1_sg_x3 <= ce_1;
  clk_1_sg_x3 <= clk_1;
  expres4g1024m_adc_user_datai2_net_x0 <= in1;
  out1 <= reinterpret_output_port_net_x6;

  concat: entity work.concat_c2ceb1b433
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      in0(0) => inverter_op_net,
      in1 => slice1_y_net,
      y => concat_y_net
    );

  inverter: entity work.inverter_2f02a7b0ae
    port map (
      ce => ce_1_sg_x3,
      clk => clk_1_sg_x3,
      clr => '0',
      ip(0) => slice_y_net,
      op(0) => inverter_op_net
    );

  reinterpret: entity work.reinterpret_b4b31b4648
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      input_port => concat_y_net,
      output_port => reinterpret_output_port_net_x6
    );

  slice: entity work.slice_1145e8f1a6
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      x => expres4g1024m_adc_user_datai2_net_x0,
      y(0) => slice_y_net
    );

  slice1: entity work.slice1_30272eab40
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      x => expres4g1024m_adc_user_datai2_net_x0,
      y => slice1_y_net
    );

end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;

-- Generated from Simulink block "expres4g1024M/adc/conv3"

entity conv3_entity_96c1e66e28 is
  port (
    ce_1: in std_logic;
    clk_1: in std_logic;
    in1: in std_logic_vector(7 downto 0);
    out1: out std_logic_vector(7 downto 0)
  );
end conv3_entity_96c1e66e28;

architecture structural of conv3_entity_96c1e66e28 is
  signal ce_1_sg_x4: std_logic;
  signal clk_1_sg_x4: std_logic;
  signal concat_y_net: std_logic_vector(7 downto 0);
  signal expres4g1024m_adc_user_datai3_net_x0: std_logic_vector(7 downto 0);
  signal inverter_op_net: std_logic;
  signal reinterpret_output_port_net_x7: std_logic_vector(7 downto 0);
  signal slice1_y_net: std_logic_vector(6 downto 0);
  signal slice_y_net: std_logic;

begin
  ce_1_sg_x4 <= ce_1;
  clk_1_sg_x4 <= clk_1;
  expres4g1024m_adc_user_datai3_net_x0 <= in1;
  out1 <= reinterpret_output_port_net_x7;

  concat: entity work.concat_f31155dc36
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      in0(0) => inverter_op_net,
      in1 => slice1_y_net,
      y => concat_y_net
    );

  inverter: entity work.inverter_deb105cfd5
    port map (
      ce => ce_1_sg_x4,
      clk => clk_1_sg_x4,
      clr => '0',
      ip(0) => slice_y_net,
      op(0) => inverter_op_net
    );

  reinterpret: entity work.reinterpret_1953f27fdf
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      input_port => concat_y_net,
      output_port => reinterpret_output_port_net_x7
    );

  slice: entity work.slice_17b71bf882
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      x => expres4g1024m_adc_user_datai3_net_x0,
      y(0) => slice_y_net
    );

  slice1: entity work.slice1_b8da15b44a
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      x => expres4g1024m_adc_user_datai3_net_x0,
      y => slice1_y_net
    );

end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;

-- Generated from Simulink block "expres4g1024M/adc/conv4"

entity conv4_entity_91fe140263 is
  port (
    ce_1: in std_logic;
    clk_1: in std_logic;
    in1: in std_logic_vector(7 downto 0);
    out1: out std_logic_vector(7 downto 0)
  );
end conv4_entity_91fe140263;

architecture structural of conv4_entity_91fe140263 is
  signal ce_1_sg_x5: std_logic;
  signal clk_1_sg_x5: std_logic;
  signal concat_y_net: std_logic_vector(7 downto 0);
  signal expres4g1024m_adc_user_dataq0_net_x0: std_logic_vector(7 downto 0);
  signal inverter_op_net: std_logic;
  signal reinterpret_output_port_net_x4: std_logic_vector(7 downto 0);
  signal slice1_y_net: std_logic_vector(6 downto 0);
  signal slice_y_net: std_logic;

begin
  ce_1_sg_x5 <= ce_1;
  clk_1_sg_x5 <= clk_1;
  expres4g1024m_adc_user_dataq0_net_x0 <= in1;
  out1 <= reinterpret_output_port_net_x4;

  concat: entity work.concat_8f2a4bed20
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      in0(0) => inverter_op_net,
      in1 => slice1_y_net,
      y => concat_y_net
    );

  inverter: entity work.inverter_f6278b222a
    port map (
      ce => ce_1_sg_x5,
      clk => clk_1_sg_x5,
      clr => '0',
      ip(0) => slice_y_net,
      op(0) => inverter_op_net
    );

  reinterpret: entity work.reinterpret_28813488a0
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      input_port => concat_y_net,
      output_port => reinterpret_output_port_net_x4
    );

  slice: entity work.slice_4086228a71
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      x => expres4g1024m_adc_user_dataq0_net_x0,
      y(0) => slice_y_net
    );

  slice1: entity work.slice1_dc1027beb6
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      x => expres4g1024m_adc_user_dataq0_net_x0,
      y => slice1_y_net
    );

end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;

-- Generated from Simulink block "expres4g1024M/adc/conv5"

entity conv5_entity_d456057b01 is
  port (
    ce_1: in std_logic;
    clk_1: in std_logic;
    in1: in std_logic_vector(7 downto 0);
    out1: out std_logic_vector(7 downto 0)
  );
end conv5_entity_d456057b01;

architecture structural of conv5_entity_d456057b01 is
  signal ce_1_sg_x6: std_logic;
  signal clk_1_sg_x6: std_logic;
  signal concat_y_net: std_logic_vector(7 downto 0);
  signal expres4g1024m_adc_user_dataq1_net_x0: std_logic_vector(7 downto 0);
  signal inverter_op_net: std_logic;
  signal reinterpret_output_port_net_x5: std_logic_vector(7 downto 0);
  signal slice1_y_net: std_logic_vector(6 downto 0);
  signal slice_y_net: std_logic;

begin
  ce_1_sg_x6 <= ce_1;
  clk_1_sg_x6 <= clk_1;
  expres4g1024m_adc_user_dataq1_net_x0 <= in1;
  out1 <= reinterpret_output_port_net_x5;

  concat: entity work.concat_c6213979ad
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      in0(0) => inverter_op_net,
      in1 => slice1_y_net,
      y => concat_y_net
    );

  inverter: entity work.inverter_14e3210e70
    port map (
      ce => ce_1_sg_x6,
      clk => clk_1_sg_x6,
      clr => '0',
      ip(0) => slice_y_net,
      op(0) => inverter_op_net
    );

  reinterpret: entity work.reinterpret_c607a35a29
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      input_port => concat_y_net,
      output_port => reinterpret_output_port_net_x5
    );

  slice: entity work.slice_d1e6bddb3b
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      x => expres4g1024m_adc_user_dataq1_net_x0,
      y(0) => slice_y_net
    );

  slice1: entity work.slice1_c85fcf892b
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      x => expres4g1024m_adc_user_dataq1_net_x0,
      y => slice1_y_net
    );

end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;

-- Generated from Simulink block "expres4g1024M/adc/conv6"

entity conv6_entity_98cfaee0c2 is
  port (
    ce_1: in std_logic;
    clk_1: in std_logic;
    in1: in std_logic_vector(7 downto 0);
    out1: out std_logic_vector(7 downto 0)
  );
end conv6_entity_98cfaee0c2;

architecture structural of conv6_entity_98cfaee0c2 is
  signal ce_1_sg_x7: std_logic;
  signal clk_1_sg_x7: std_logic;
  signal concat_y_net: std_logic_vector(7 downto 0);
  signal expres4g1024m_adc_user_dataq2_net_x0: std_logic_vector(7 downto 0);
  signal inverter_op_net: std_logic;
  signal reinterpret_output_port_net_x6: std_logic_vector(7 downto 0);
  signal slice1_y_net: std_logic_vector(6 downto 0);
  signal slice_y_net: std_logic;

begin
  ce_1_sg_x7 <= ce_1;
  clk_1_sg_x7 <= clk_1;
  expres4g1024m_adc_user_dataq2_net_x0 <= in1;
  out1 <= reinterpret_output_port_net_x6;

  concat: entity work.concat_abceb0e700
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      in0(0) => inverter_op_net,
      in1 => slice1_y_net,
      y => concat_y_net
    );

  inverter: entity work.inverter_1583af95f1
    port map (
      ce => ce_1_sg_x7,
      clk => clk_1_sg_x7,
      clr => '0',
      ip(0) => slice_y_net,
      op(0) => inverter_op_net
    );

  reinterpret: entity work.reinterpret_7eef37775d
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      input_port => concat_y_net,
      output_port => reinterpret_output_port_net_x6
    );

  slice: entity work.slice_58a5b34657
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      x => expres4g1024m_adc_user_dataq2_net_x0,
      y(0) => slice_y_net
    );

  slice1: entity work.slice1_94a4a96ba5
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      x => expres4g1024m_adc_user_dataq2_net_x0,
      y => slice1_y_net
    );

end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;

-- Generated from Simulink block "expres4g1024M/adc/conv7"

entity conv7_entity_c2e26db709 is
  port (
    ce_1: in std_logic;
    clk_1: in std_logic;
    in1: in std_logic_vector(7 downto 0);
    out1: out std_logic_vector(7 downto 0)
  );
end conv7_entity_c2e26db709;

architecture structural of conv7_entity_c2e26db709 is
  signal ce_1_sg_x8: std_logic;
  signal clk_1_sg_x8: std_logic;
  signal concat_y_net: std_logic_vector(7 downto 0);
  signal expres4g1024m_adc_user_dataq3_net_x0: std_logic_vector(7 downto 0);
  signal inverter_op_net: std_logic;
  signal reinterpret_output_port_net_x7: std_logic_vector(7 downto 0);
  signal slice1_y_net: std_logic_vector(6 downto 0);
  signal slice_y_net: std_logic;

begin
  ce_1_sg_x8 <= ce_1;
  clk_1_sg_x8 <= clk_1;
  expres4g1024m_adc_user_dataq3_net_x0 <= in1;
  out1 <= reinterpret_output_port_net_x7;

  concat: entity work.concat_c79d543ed9
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      in0(0) => inverter_op_net,
      in1 => slice1_y_net,
      y => concat_y_net
    );

  inverter: entity work.inverter_8ce249e4c9
    port map (
      ce => ce_1_sg_x8,
      clk => clk_1_sg_x8,
      clr => '0',
      ip(0) => slice_y_net,
      op(0) => inverter_op_net
    );

  reinterpret: entity work.reinterpret_955f8abbef
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      input_port => concat_y_net,
      output_port => reinterpret_output_port_net_x7
    );

  slice: entity work.slice_510bfcefde
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      x => expres4g1024m_adc_user_dataq3_net_x0,
      y(0) => slice_y_net
    );

  slice1: entity work.slice1_a788d95eec
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      x => expres4g1024m_adc_user_dataq3_net_x0,
      y => slice1_y_net
    );

end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;

-- Generated from Simulink block "expres4g1024M/adc"

entity adc_entity_9852d04a8e is
  port (
    ce_1: in std_logic;
    clk_1: in std_logic;
    expres4g1024m_adc_user_datai0: in std_logic_vector(7 downto 0);
    expres4g1024m_adc_user_datai1: in std_logic_vector(7 downto 0);
    expres4g1024m_adc_user_datai2: in std_logic_vector(7 downto 0);
    expres4g1024m_adc_user_datai3: in std_logic_vector(7 downto 0);
    expres4g1024m_adc_user_dataq0: in std_logic_vector(7 downto 0);
    expres4g1024m_adc_user_dataq1: in std_logic_vector(7 downto 0);
    expres4g1024m_adc_user_dataq2: in std_logic_vector(7 downto 0);
    expres4g1024m_adc_user_dataq3: in std_logic_vector(7 downto 0);
    i0: out std_logic_vector(7 downto 0);
    i1: out std_logic_vector(7 downto 0);
    i2: out std_logic_vector(7 downto 0);
    i3: out std_logic_vector(7 downto 0);
    q0: out std_logic_vector(7 downto 0);
    q1: out std_logic_vector(7 downto 0);
    q2: out std_logic_vector(7 downto 0);
    q3: out std_logic_vector(7 downto 0)
  );
end adc_entity_9852d04a8e;

architecture structural of adc_entity_9852d04a8e is
  signal ce_1_sg_x9: std_logic;
  signal clk_1_sg_x9: std_logic;
  signal expres4g1024m_adc_user_datai0_net_x1: std_logic_vector(7 downto 0);
  signal expres4g1024m_adc_user_datai1_net_x1: std_logic_vector(7 downto 0);
  signal expres4g1024m_adc_user_datai2_net_x1: std_logic_vector(7 downto 0);
  signal expres4g1024m_adc_user_datai3_net_x1: std_logic_vector(7 downto 0);
  signal expres4g1024m_adc_user_dataq0_net_x1: std_logic_vector(7 downto 0);
  signal expres4g1024m_adc_user_dataq1_net_x1: std_logic_vector(7 downto 0);
  signal expres4g1024m_adc_user_dataq2_net_x1: std_logic_vector(7 downto 0);
  signal expres4g1024m_adc_user_dataq3_net_x1: std_logic_vector(7 downto 0);
  signal reinterpret_output_port_net_x12: std_logic_vector(7 downto 0);
  signal reinterpret_output_port_net_x13: std_logic_vector(7 downto 0);
  signal reinterpret_output_port_net_x14: std_logic_vector(7 downto 0);
  signal reinterpret_output_port_net_x15: std_logic_vector(7 downto 0);
  signal reinterpret_output_port_net_x16: std_logic_vector(7 downto 0);
  signal reinterpret_output_port_net_x17: std_logic_vector(7 downto 0);
  signal reinterpret_output_port_net_x18: std_logic_vector(7 downto 0);
  signal reinterpret_output_port_net_x19: std_logic_vector(7 downto 0);

begin
  ce_1_sg_x9 <= ce_1;
  clk_1_sg_x9 <= clk_1;
  expres4g1024m_adc_user_datai0_net_x1 <= expres4g1024m_adc_user_datai0;
  expres4g1024m_adc_user_datai1_net_x1 <= expres4g1024m_adc_user_datai1;
  expres4g1024m_adc_user_datai2_net_x1 <= expres4g1024m_adc_user_datai2;
  expres4g1024m_adc_user_datai3_net_x1 <= expres4g1024m_adc_user_datai3;
  expres4g1024m_adc_user_dataq0_net_x1 <= expres4g1024m_adc_user_dataq0;
  expres4g1024m_adc_user_dataq1_net_x1 <= expres4g1024m_adc_user_dataq1;
  expres4g1024m_adc_user_dataq2_net_x1 <= expres4g1024m_adc_user_dataq2;
  expres4g1024m_adc_user_dataq3_net_x1 <= expres4g1024m_adc_user_dataq3;
  i0 <= reinterpret_output_port_net_x12;
  i1 <= reinterpret_output_port_net_x13;
  i2 <= reinterpret_output_port_net_x14;
  i3 <= reinterpret_output_port_net_x15;
  q0 <= reinterpret_output_port_net_x16;
  q1 <= reinterpret_output_port_net_x17;
  q2 <= reinterpret_output_port_net_x18;
  q3 <= reinterpret_output_port_net_x19;

  conv1_99e0255406: entity work.conv1_entity_99e0255406
    port map (
      ce_1 => ce_1_sg_x9,
      clk_1 => clk_1_sg_x9,
      in1 => expres4g1024m_adc_user_datai1_net_x1,
      out1 => reinterpret_output_port_net_x13
    );

  conv2_8ea5768454: entity work.conv2_entity_8ea5768454
    port map (
      ce_1 => ce_1_sg_x9,
      clk_1 => clk_1_sg_x9,
      in1 => expres4g1024m_adc_user_datai2_net_x1,
      out1 => reinterpret_output_port_net_x14
    );

  conv3_96c1e66e28: entity work.conv3_entity_96c1e66e28
    port map (
      ce_1 => ce_1_sg_x9,
      clk_1 => clk_1_sg_x9,
      in1 => expres4g1024m_adc_user_datai3_net_x1,
      out1 => reinterpret_output_port_net_x15
    );

  conv4_91fe140263: entity work.conv4_entity_91fe140263
    port map (
      ce_1 => ce_1_sg_x9,
      clk_1 => clk_1_sg_x9,
      in1 => expres4g1024m_adc_user_dataq0_net_x1,
      out1 => reinterpret_output_port_net_x16
    );

  conv5_d456057b01: entity work.conv5_entity_d456057b01
    port map (
      ce_1 => ce_1_sg_x9,
      clk_1 => clk_1_sg_x9,
      in1 => expres4g1024m_adc_user_dataq1_net_x1,
      out1 => reinterpret_output_port_net_x17
    );

  conv6_98cfaee0c2: entity work.conv6_entity_98cfaee0c2
    port map (
      ce_1 => ce_1_sg_x9,
      clk_1 => clk_1_sg_x9,
      in1 => expres4g1024m_adc_user_dataq2_net_x1,
      out1 => reinterpret_output_port_net_x18
    );

  conv7_c2e26db709: entity work.conv7_entity_c2e26db709
    port map (
      ce_1 => ce_1_sg_x9,
      clk_1 => clk_1_sg_x9,
      in1 => expres4g1024m_adc_user_dataq3_net_x1,
      out1 => reinterpret_output_port_net_x19
    );

  conv_f5df0b0e65: entity work.conv_entity_f5df0b0e65
    port map (
      ce_1 => ce_1_sg_x9,
      clk_1 => clk_1_sg_x9,
      in1 => expres4g1024m_adc_user_datai0_net_x1,
      out1 => reinterpret_output_port_net_x12
    );

end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;

-- Generated from Simulink block "expres4g1024M/adc_data_i"

entity adc_data_i_entity_a3a8938725 is
  port (
    reg_out: in std_logic_vector(31 downto 0);
    convert_x0: out std_logic_vector(31 downto 0)
  );
end adc_data_i_entity_a3a8938725;

architecture structural of adc_data_i_entity_a3a8938725 is
  signal convert_dout_net_x0: std_logic_vector(31 downto 0);
  signal dly13_q_net_x0: std_logic_vector(31 downto 0);

begin
  dly13_q_net_x0 <= reg_out;
  convert_x0 <= convert_dout_net_x0;

  convert: entity work.xlconvert
    generic map (
      bool_conversion => 0,
      din_arith => 1,
      din_bin_pt => 0,
      din_width => 32,
      dout_arith => 1,
      dout_bin_pt => 0,
      dout_width => 32,
      latency => 0,
      overflow => xlWrap,
      quantization => xlTruncate
    )
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      din => dly13_q_net_x0,
      dout => convert_dout_net_x0
    );

end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;

-- Generated from Simulink block "expres4g1024M/adc_data_q"

entity adc_data_q_entity_64b50d7ffe is
  port (
    reg_out: in std_logic_vector(31 downto 0);
    convert_x0: out std_logic_vector(31 downto 0)
  );
end adc_data_q_entity_64b50d7ffe;

architecture structural of adc_data_q_entity_64b50d7ffe is
  signal convert_dout_net_x0: std_logic_vector(31 downto 0);
  signal dly27_q_net_x0: std_logic_vector(31 downto 0);

begin
  dly27_q_net_x0 <= reg_out;
  convert_x0 <= convert_dout_net_x0;

  convert: entity work.xlconvert
    generic map (
      bool_conversion => 0,
      din_arith => 1,
      din_bin_pt => 0,
      din_width => 32,
      dout_arith => 1,
      dout_bin_pt => 0,
      dout_width => 32,
      latency => 0,
      overflow => xlWrap,
      quantization => xlTruncate
    )
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      din => dly27_q_net_x0,
      dout => convert_dout_net_x0
    );

end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;

-- Generated from Simulink block "expres4g1024M/led0"

entity led0_entity_adcb04e180 is
  port (
    gpio_out: in std_logic;
    convert_x0: out std_logic
  );
end led0_entity_adcb04e180;

architecture structural of led0_entity_adcb04e180 is
  signal convert_dout_net_x0: std_logic;
  signal expres4g1024m_ten_gbe2_led_rx_net_x0: std_logic;

begin
  expres4g1024m_ten_gbe2_led_rx_net_x0 <= gpio_out;
  convert_x0 <= convert_dout_net_x0;

  convert: entity work.xlconvert
    generic map (
      bool_conversion => 1,
      din_arith => 1,
      din_bin_pt => 0,
      din_width => 1,
      dout_arith => 1,
      dout_bin_pt => 0,
      dout_width => 1,
      latency => 0,
      overflow => xlWrap,
      quantization => xlTruncate
    )
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      din(0) => expres4g1024m_ten_gbe2_led_rx_net_x0,
      dout(0) => convert_dout_net_x0
    );

end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;

-- Generated from Simulink block "expres4g1024M/led1"

entity led1_entity_6df427b2a9 is
  port (
    gpio_out: in std_logic;
    convert_x0: out std_logic
  );
end led1_entity_6df427b2a9;

architecture structural of led1_entity_6df427b2a9 is
  signal convert_dout_net_x0: std_logic;
  signal expres4g1024m_ten_gbe2_led_tx_net_x0: std_logic;

begin
  expres4g1024m_ten_gbe2_led_tx_net_x0 <= gpio_out;
  convert_x0 <= convert_dout_net_x0;

  convert: entity work.xlconvert
    generic map (
      bool_conversion => 1,
      din_arith => 1,
      din_bin_pt => 0,
      din_width => 1,
      dout_arith => 1,
      dout_bin_pt => 0,
      dout_width => 1,
      latency => 0,
      overflow => xlWrap,
      quantization => xlTruncate
    )
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      din(0) => expres4g1024m_ten_gbe2_led_tx_net_x0,
      dout(0) => convert_dout_net_x0
    );

end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;

-- Generated from Simulink block "expres4g1024M/led2"

entity led2_entity_a89ed2d92f is
  port (
    gpio_out: in std_logic;
    convert_x0: out std_logic
  );
end led2_entity_a89ed2d92f;

architecture structural of led2_entity_a89ed2d92f is
  signal convert_dout_net_x0: std_logic;
  signal expres4g1024m_ten_gbe1_led_rx_net_x0: std_logic;

begin
  expres4g1024m_ten_gbe1_led_rx_net_x0 <= gpio_out;
  convert_x0 <= convert_dout_net_x0;

  convert: entity work.xlconvert
    generic map (
      bool_conversion => 1,
      din_arith => 1,
      din_bin_pt => 0,
      din_width => 1,
      dout_arith => 1,
      dout_bin_pt => 0,
      dout_width => 1,
      latency => 0,
      overflow => xlWrap,
      quantization => xlTruncate
    )
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      din(0) => expres4g1024m_ten_gbe1_led_rx_net_x0,
      dout(0) => convert_dout_net_x0
    );

end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;

-- Generated from Simulink block "expres4g1024M/led3"

entity led3_entity_de4918e802 is
  port (
    gpio_out: in std_logic;
    convert_x0: out std_logic
  );
end led3_entity_de4918e802;

architecture structural of led3_entity_de4918e802 is
  signal convert_dout_net_x0: std_logic;
  signal expres4g1024m_ten_gbe1_led_tx_net_x0: std_logic;

begin
  expres4g1024m_ten_gbe1_led_tx_net_x0 <= gpio_out;
  convert_x0 <= convert_dout_net_x0;

  convert: entity work.xlconvert
    generic map (
      bool_conversion => 1,
      din_arith => 1,
      din_bin_pt => 0,
      din_width => 1,
      dout_arith => 1,
      dout_bin_pt => 0,
      dout_width => 1,
      latency => 0,
      overflow => xlWrap,
      quantization => xlTruncate
    )
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      din(0) => expres4g1024m_ten_gbe1_led_tx_net_x0,
      dout(0) => convert_dout_net_x0
    );

end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;

-- Generated from Simulink block "expres4g1024M/led6"

entity led6_entity_89f383e74d is
  port (
    gpio_out: in std_logic;
    convert_x0: out std_logic
  );
end led6_entity_89f383e74d;

architecture structural of led6_entity_89f383e74d is
  signal convert_dout_net_x0: std_logic;
  signal dly11_q_net_x0: std_logic;

begin
  dly11_q_net_x0 <= gpio_out;
  convert_x0 <= convert_dout_net_x0;

  convert: entity work.xlconvert
    generic map (
      bool_conversion => 1,
      din_arith => 1,
      din_bin_pt => 0,
      din_width => 1,
      dout_arith => 1,
      dout_bin_pt => 0,
      dout_width => 1,
      latency => 0,
      overflow => xlWrap,
      quantization => xlTruncate
    )
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      din(0) => dly11_q_net_x0,
      dout(0) => convert_dout_net_x0
    );

end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;

-- Generated from Simulink block "expres4g1024M/led7"

entity led7_entity_fc9cf74af9 is
  port (
    gpio_out: in std_logic;
    convert_x0: out std_logic
  );
end led7_entity_fc9cf74af9;

architecture structural of led7_entity_fc9cf74af9 is
  signal convert_dout_net_x0: std_logic;
  signal dly18_q_net_x0: std_logic;

begin
  dly18_q_net_x0 <= gpio_out;
  convert_x0 <= convert_dout_net_x0;

  convert: entity work.xlconvert
    generic map (
      bool_conversion => 1,
      din_arith => 1,
      din_bin_pt => 0,
      din_width => 1,
      dout_arith => 1,
      dout_bin_pt => 0,
      dout_width => 1,
      latency => 0,
      overflow => xlWrap,
      quantization => xlTruncate
    )
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      din(0) => dly18_q_net_x0,
      dout(0) => convert_dout_net_x0
    );

end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;

-- Generated from Simulink block "expres4g1024M/rtc_time"

entity rtc_time_entity_e8033653dc is
  port (
    reg_out: in std_logic_vector(31 downto 0);
    convert_x0: out std_logic_vector(31 downto 0)
  );
end rtc_time_entity_e8033653dc;

architecture structural of rtc_time_entity_e8033653dc is
  signal convert_dout_net_x0: std_logic_vector(31 downto 0);
  signal dly10_q_net_x0: std_logic_vector(31 downto 0);

begin
  dly10_q_net_x0 <= reg_out;
  convert_x0 <= convert_dout_net_x0;

  convert: entity work.xlconvert
    generic map (
      bool_conversion => 0,
      din_arith => 1,
      din_bin_pt => 0,
      din_width => 32,
      dout_arith => 1,
      dout_bin_pt => 0,
      dout_width => 32,
      latency => 0,
      overflow => xlWrap,
      quantization => xlTruncate
    )
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      din => dly10_q_net_x0,
      dout => convert_dout_net_x0
    );

end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;

-- Generated from Simulink block "expres4g1024M/status"

entity status_entity_c438123aa7 is
  port (
    reg_out: in std_logic_vector(91 downto 0);
    convert_x0: out std_logic_vector(31 downto 0)
  );
end status_entity_c438123aa7;

architecture structural of status_entity_c438123aa7 is
  signal convert_dout_net_x0: std_logic_vector(31 downto 0);
  signal dly7_q_net_x0: std_logic_vector(91 downto 0);

begin
  dly7_q_net_x0 <= reg_out;
  convert_x0 <= convert_dout_net_x0;

  convert: entity work.xlconvert
    generic map (
      bool_conversion => 0,
      din_arith => 1,
      din_bin_pt => 0,
      din_width => 92,
      dout_arith => 1,
      dout_bin_pt => 0,
      dout_width => 32,
      latency => 0,
      overflow => xlWrap,
      quantization => xlTruncate
    )
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      din => dly7_q_net_x0,
      dout => convert_dout_net_x0
    );

end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;

-- Generated from Simulink block "expres4g1024M/ten_GbE1"

entity ten_gbe1_entity_b0a1ef16c5 is
  port (
    rst: in std_logic;
    rx_ack: in std_logic;
    tx_data: in std_logic_vector(63 downto 0);
    tx_dest_ip: in std_logic_vector(31 downto 0);
    tx_dest_port: in std_logic_vector(32 downto 0);
    tx_discard: in std_logic;
    tx_end_of_frame: in std_logic;
    tx_valid: in std_logic;
    convert_rst_x0: out std_logic;
    convert_rx_ack_x0: out std_logic;
    convert_tx_data_x0: out std_logic_vector(63 downto 0);
    convert_tx_dest_ip_x0: out std_logic_vector(31 downto 0);
    convert_tx_discard_x0: out std_logic;
    convert_tx_end_of_frame_x0: out std_logic;
    convert_tx_port_x0: out std_logic_vector(15 downto 0);
    convert_tx_valid_x0: out std_logic
  );
end ten_gbe1_entity_b0a1ef16c5;

architecture structural of ten_gbe1_entity_b0a1ef16c5 is
  signal convert_rst_dout_net_x0: std_logic;
  signal convert_rx_ack_dout_net_x0: std_logic;
  signal convert_tx_data_dout_net_x0: std_logic_vector(63 downto 0);
  signal convert_tx_dest_ip_dout_net_x0: std_logic_vector(31 downto 0);
  signal convert_tx_discard_dout_net_x0: std_logic;
  signal convert_tx_end_of_frame_dout_net_x0: std_logic;
  signal convert_tx_port_dout_net_x0: std_logic_vector(15 downto 0);
  signal convert_tx_valid_dout_net_x0: std_logic;
  signal dly20_q_net_x0: std_logic_vector(63 downto 0);
  signal dly21_q_net_x0: std_logic;
  signal dly22_q_net_x0: std_logic;
  signal dly23_q_net_x0: std_logic;
  signal dly24_q_net_x0: std_logic_vector(31 downto 0);
  signal dly25_q_net_x0: std_logic_vector(32 downto 0);
  signal dly26_q_net_x0: std_logic;
  signal expres4g1024m_ten_gbe1_rx_valid_net_x0: std_logic;

begin
  dly26_q_net_x0 <= rst;
  expres4g1024m_ten_gbe1_rx_valid_net_x0 <= rx_ack;
  dly20_q_net_x0 <= tx_data;
  dly24_q_net_x0 <= tx_dest_ip;
  dly25_q_net_x0 <= tx_dest_port;
  dly23_q_net_x0 <= tx_discard;
  dly22_q_net_x0 <= tx_end_of_frame;
  dly21_q_net_x0 <= tx_valid;
  convert_rst_x0 <= convert_rst_dout_net_x0;
  convert_rx_ack_x0 <= convert_rx_ack_dout_net_x0;
  convert_tx_data_x0 <= convert_tx_data_dout_net_x0;
  convert_tx_dest_ip_x0 <= convert_tx_dest_ip_dout_net_x0;
  convert_tx_discard_x0 <= convert_tx_discard_dout_net_x0;
  convert_tx_end_of_frame_x0 <= convert_tx_end_of_frame_dout_net_x0;
  convert_tx_port_x0 <= convert_tx_port_dout_net_x0;
  convert_tx_valid_x0 <= convert_tx_valid_dout_net_x0;

  convert_rst: entity work.xlconvert
    generic map (
      bool_conversion => 1,
      din_arith => 1,
      din_bin_pt => 0,
      din_width => 1,
      dout_arith => 1,
      dout_bin_pt => 0,
      dout_width => 1,
      latency => 0,
      overflow => xlWrap,
      quantization => xlTruncate
    )
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      din(0) => dly26_q_net_x0,
      dout(0) => convert_rst_dout_net_x0
    );

  convert_rx_ack: entity work.xlconvert
    generic map (
      bool_conversion => 1,
      din_arith => 1,
      din_bin_pt => 0,
      din_width => 1,
      dout_arith => 1,
      dout_bin_pt => 0,
      dout_width => 1,
      latency => 0,
      overflow => xlWrap,
      quantization => xlTruncate
    )
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      din(0) => expres4g1024m_ten_gbe1_rx_valid_net_x0,
      dout(0) => convert_rx_ack_dout_net_x0
    );

  convert_tx_data: entity work.xlconvert
    generic map (
      bool_conversion => 0,
      din_arith => 1,
      din_bin_pt => 0,
      din_width => 64,
      dout_arith => 1,
      dout_bin_pt => 0,
      dout_width => 64,
      latency => 0,
      overflow => xlWrap,
      quantization => xlTruncate
    )
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      din => dly20_q_net_x0,
      dout => convert_tx_data_dout_net_x0
    );

  convert_tx_dest_ip: entity work.xlconvert
    generic map (
      bool_conversion => 0,
      din_arith => 1,
      din_bin_pt => 0,
      din_width => 32,
      dout_arith => 1,
      dout_bin_pt => 0,
      dout_width => 32,
      latency => 0,
      overflow => xlWrap,
      quantization => xlTruncate
    )
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      din => dly24_q_net_x0,
      dout => convert_tx_dest_ip_dout_net_x0
    );

  convert_tx_discard: entity work.xlconvert
    generic map (
      bool_conversion => 1,
      din_arith => 1,
      din_bin_pt => 0,
      din_width => 1,
      dout_arith => 1,
      dout_bin_pt => 0,
      dout_width => 1,
      latency => 0,
      overflow => xlWrap,
      quantization => xlTruncate
    )
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      din(0) => dly23_q_net_x0,
      dout(0) => convert_tx_discard_dout_net_x0
    );

  convert_tx_end_of_frame: entity work.xlconvert
    generic map (
      bool_conversion => 1,
      din_arith => 1,
      din_bin_pt => 0,
      din_width => 1,
      dout_arith => 1,
      dout_bin_pt => 0,
      dout_width => 1,
      latency => 0,
      overflow => xlWrap,
      quantization => xlTruncate
    )
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      din(0) => dly22_q_net_x0,
      dout(0) => convert_tx_end_of_frame_dout_net_x0
    );

  convert_tx_port: entity work.xlconvert
    generic map (
      bool_conversion => 0,
      din_arith => 1,
      din_bin_pt => 0,
      din_width => 33,
      dout_arith => 1,
      dout_bin_pt => 0,
      dout_width => 16,
      latency => 0,
      overflow => xlWrap,
      quantization => xlTruncate
    )
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      din => dly25_q_net_x0,
      dout => convert_tx_port_dout_net_x0
    );

  convert_tx_valid: entity work.xlconvert
    generic map (
      bool_conversion => 1,
      din_arith => 1,
      din_bin_pt => 0,
      din_width => 1,
      dout_arith => 1,
      dout_bin_pt => 0,
      dout_width => 1,
      latency => 0,
      overflow => xlWrap,
      quantization => xlTruncate
    )
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      din(0) => dly21_q_net_x0,
      dout(0) => convert_tx_valid_dout_net_x0
    );

end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;

-- Generated from Simulink block "expres4g1024M/ten_GbE2"

entity ten_gbe2_entity_ddd9f696b9 is
  port (
    rst: in std_logic;
    rx_ack: in std_logic;
    tx_data: in std_logic_vector(63 downto 0);
    tx_dest_ip: in std_logic_vector(31 downto 0);
    tx_dest_port: in std_logic_vector(31 downto 0);
    tx_discard: in std_logic;
    tx_end_of_frame: in std_logic;
    tx_valid: in std_logic;
    convert_rst_x0: out std_logic;
    convert_rx_ack_x0: out std_logic;
    convert_tx_data_x0: out std_logic_vector(63 downto 0);
    convert_tx_dest_ip_x0: out std_logic_vector(31 downto 0);
    convert_tx_discard_x0: out std_logic;
    convert_tx_end_of_frame_x0: out std_logic;
    convert_tx_port_x0: out std_logic_vector(15 downto 0);
    convert_tx_valid_x0: out std_logic
  );
end ten_gbe2_entity_ddd9f696b9;

architecture structural of ten_gbe2_entity_ddd9f696b9 is
  signal convert_rst_dout_net_x0: std_logic;
  signal convert_rx_ack_dout_net_x0: std_logic;
  signal convert_tx_data_dout_net_x0: std_logic_vector(63 downto 0);
  signal convert_tx_dest_ip_dout_net_x0: std_logic_vector(31 downto 0);
  signal convert_tx_discard_dout_net_x0: std_logic;
  signal convert_tx_end_of_frame_dout_net_x0: std_logic;
  signal convert_tx_port_dout_net_x0: std_logic_vector(15 downto 0);
  signal convert_tx_valid_dout_net_x0: std_logic;
  signal dly1_q_net_x0: std_logic;
  signal dly2_q_net_x0: std_logic;
  signal dly3_q_net_x0: std_logic;
  signal dly4_q_net_x0: std_logic_vector(31 downto 0);
  signal dly5_q_net_x0: std_logic_vector(31 downto 0);
  signal dly8_q_net_x0: std_logic;
  signal dly_q_net_x0: std_logic_vector(63 downto 0);
  signal expres4g1024m_ten_gbe2_rx_valid_net_x0: std_logic;

begin
  dly8_q_net_x0 <= rst;
  expres4g1024m_ten_gbe2_rx_valid_net_x0 <= rx_ack;
  dly_q_net_x0 <= tx_data;
  dly4_q_net_x0 <= tx_dest_ip;
  dly5_q_net_x0 <= tx_dest_port;
  dly3_q_net_x0 <= tx_discard;
  dly2_q_net_x0 <= tx_end_of_frame;
  dly1_q_net_x0 <= tx_valid;
  convert_rst_x0 <= convert_rst_dout_net_x0;
  convert_rx_ack_x0 <= convert_rx_ack_dout_net_x0;
  convert_tx_data_x0 <= convert_tx_data_dout_net_x0;
  convert_tx_dest_ip_x0 <= convert_tx_dest_ip_dout_net_x0;
  convert_tx_discard_x0 <= convert_tx_discard_dout_net_x0;
  convert_tx_end_of_frame_x0 <= convert_tx_end_of_frame_dout_net_x0;
  convert_tx_port_x0 <= convert_tx_port_dout_net_x0;
  convert_tx_valid_x0 <= convert_tx_valid_dout_net_x0;

  convert_rst: entity work.xlconvert
    generic map (
      bool_conversion => 1,
      din_arith => 1,
      din_bin_pt => 0,
      din_width => 1,
      dout_arith => 1,
      dout_bin_pt => 0,
      dout_width => 1,
      latency => 0,
      overflow => xlWrap,
      quantization => xlTruncate
    )
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      din(0) => dly8_q_net_x0,
      dout(0) => convert_rst_dout_net_x0
    );

  convert_rx_ack: entity work.xlconvert
    generic map (
      bool_conversion => 1,
      din_arith => 1,
      din_bin_pt => 0,
      din_width => 1,
      dout_arith => 1,
      dout_bin_pt => 0,
      dout_width => 1,
      latency => 0,
      overflow => xlWrap,
      quantization => xlTruncate
    )
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      din(0) => expres4g1024m_ten_gbe2_rx_valid_net_x0,
      dout(0) => convert_rx_ack_dout_net_x0
    );

  convert_tx_data: entity work.xlconvert
    generic map (
      bool_conversion => 0,
      din_arith => 1,
      din_bin_pt => 0,
      din_width => 64,
      dout_arith => 1,
      dout_bin_pt => 0,
      dout_width => 64,
      latency => 0,
      overflow => xlWrap,
      quantization => xlTruncate
    )
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      din => dly_q_net_x0,
      dout => convert_tx_data_dout_net_x0
    );

  convert_tx_dest_ip: entity work.xlconvert
    generic map (
      bool_conversion => 0,
      din_arith => 1,
      din_bin_pt => 0,
      din_width => 32,
      dout_arith => 1,
      dout_bin_pt => 0,
      dout_width => 32,
      latency => 0,
      overflow => xlWrap,
      quantization => xlTruncate
    )
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      din => dly4_q_net_x0,
      dout => convert_tx_dest_ip_dout_net_x0
    );

  convert_tx_discard: entity work.xlconvert
    generic map (
      bool_conversion => 1,
      din_arith => 1,
      din_bin_pt => 0,
      din_width => 1,
      dout_arith => 1,
      dout_bin_pt => 0,
      dout_width => 1,
      latency => 0,
      overflow => xlWrap,
      quantization => xlTruncate
    )
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      din(0) => dly3_q_net_x0,
      dout(0) => convert_tx_discard_dout_net_x0
    );

  convert_tx_end_of_frame: entity work.xlconvert
    generic map (
      bool_conversion => 1,
      din_arith => 1,
      din_bin_pt => 0,
      din_width => 1,
      dout_arith => 1,
      dout_bin_pt => 0,
      dout_width => 1,
      latency => 0,
      overflow => xlWrap,
      quantization => xlTruncate
    )
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      din(0) => dly2_q_net_x0,
      dout(0) => convert_tx_end_of_frame_dout_net_x0
    );

  convert_tx_port: entity work.xlconvert
    generic map (
      bool_conversion => 0,
      din_arith => 1,
      din_bin_pt => 0,
      din_width => 32,
      dout_arith => 1,
      dout_bin_pt => 0,
      dout_width => 16,
      latency => 0,
      overflow => xlWrap,
      quantization => xlTruncate
    )
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      din => dly5_q_net_x0,
      dout => convert_tx_port_dout_net_x0
    );

  convert_tx_valid: entity work.xlconvert
    generic map (
      bool_conversion => 1,
      din_arith => 1,
      din_bin_pt => 0,
      din_width => 1,
      dout_arith => 1,
      dout_bin_pt => 0,
      dout_width => 1,
      latency => 0,
      overflow => xlWrap,
      quantization => xlTruncate
    )
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      din(0) => dly1_q_net_x0,
      dout(0) => convert_tx_valid_dout_net_x0
    );

end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;

-- Generated from Simulink block "expres4g1024M/twobit_data_i"

entity twobit_data_i_entity_0b92d44297 is
  port (
    reg_out: in std_logic_vector(63 downto 0);
    convert_x0: out std_logic_vector(31 downto 0)
  );
end twobit_data_i_entity_0b92d44297;

architecture structural of twobit_data_i_entity_0b92d44297 is
  signal convert_dout_net_x0: std_logic_vector(31 downto 0);
  signal register_q_net_x0: std_logic_vector(63 downto 0);

begin
  register_q_net_x0 <= reg_out;
  convert_x0 <= convert_dout_net_x0;

  convert: entity work.xlconvert
    generic map (
      bool_conversion => 0,
      din_arith => 1,
      din_bin_pt => 0,
      din_width => 64,
      dout_arith => 1,
      dout_bin_pt => 0,
      dout_width => 32,
      latency => 0,
      overflow => xlWrap,
      quantization => xlTruncate
    )
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      din => register_q_net_x0,
      dout => convert_dout_net_x0
    );

end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;

-- Generated from Simulink block "expres4g1024M/twobit_data_q"

entity twobit_data_q_entity_b7296da730 is
  port (
    reg_out: in std_logic_vector(63 downto 0);
    convert_x0: out std_logic_vector(31 downto 0)
  );
end twobit_data_q_entity_b7296da730;

architecture structural of twobit_data_q_entity_b7296da730 is
  signal convert_dout_net_x0: std_logic_vector(31 downto 0);
  signal register1_q_net_x0: std_logic_vector(63 downto 0);

begin
  register1_q_net_x0 <= reg_out;
  convert_x0 <= convert_dout_net_x0;

  convert: entity work.xlconvert
    generic map (
      bool_conversion => 0,
      din_arith => 1,
      din_bin_pt => 0,
      din_width => 64,
      dout_arith => 1,
      dout_bin_pt => 0,
      dout_width => 32,
      latency => 0,
      overflow => xlWrap,
      quantization => xlTruncate
    )
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      din => register1_q_net_x0,
      dout => convert_dout_net_x0
    );

end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;

-- Generated from Simulink block "expres4g1024M"

entity expres4g1024m is
  port (
    ce_1: in std_logic;
    clk_1: in std_logic;
    expres4g1024m_adc_user_data_valid: in std_logic;
    expres4g1024m_adc_user_datai0: in std_logic_vector(7 downto 0);
    expres4g1024m_adc_user_datai1: in std_logic_vector(7 downto 0);
    expres4g1024m_adc_user_datai2: in std_logic_vector(7 downto 0);
    expres4g1024m_adc_user_datai3: in std_logic_vector(7 downto 0);
    expres4g1024m_adc_user_dataq0: in std_logic_vector(7 downto 0);
    expres4g1024m_adc_user_dataq1: in std_logic_vector(7 downto 0);
    expres4g1024m_adc_user_dataq2: in std_logic_vector(7 downto 0);
    expres4g1024m_adc_user_dataq3: in std_logic_vector(7 downto 0);
    expres4g1024m_adc_user_outofrangei0: in std_logic;
    expres4g1024m_adc_user_outofrangei1: in std_logic;
    expres4g1024m_adc_user_outofrangeq0: in std_logic;
    expres4g1024m_adc_user_outofrangeq1: in std_logic;
    expres4g1024m_adc_user_sync0: in std_logic;
    expres4g1024m_adc_user_sync1: in std_logic;
    expres4g1024m_adc_user_sync2: in std_logic;
    expres4g1024m_adc_user_sync3: in std_logic;
    expres4g1024m_bit_levels_user_data_out: in std_logic_vector(31 downto 0);
    expres4g1024m_config_user_data_out: in std_logic_vector(31 downto 0);
    expres4g1024m_dest_ip_user_data_out: in std_logic_vector(31 downto 0);
    expres4g1024m_dest_port_offset_user_data_out: in std_logic_vector(31 downto 0);
    expres4g1024m_dest_port_user_data_out: in std_logic_vector(31 downto 0);
    expres4g1024m_national_semi_pll_user_data_out: in std_logic_vector(31 downto 0);
    expres4g1024m_rtc_settime_user_data_out: in std_logic_vector(31 downto 0);
    expres4g1024m_rtc_starttime_user_data_out: in std_logic_vector(31 downto 0);
    expres4g1024m_rtc_stoptime_user_data_out: in std_logic_vector(31 downto 0);
    expres4g1024m_ten_gbe1_led_rx: in std_logic;
    expres4g1024m_ten_gbe1_led_tx: in std_logic;
    expres4g1024m_ten_gbe1_led_up: in std_logic;
    expres4g1024m_ten_gbe1_rx_data: in std_logic_vector(63 downto 0);
    expres4g1024m_ten_gbe1_rx_end_of_frame: in std_logic;
    expres4g1024m_ten_gbe1_rx_size: in std_logic_vector(15 downto 0);
    expres4g1024m_ten_gbe1_rx_source_ip: in std_logic_vector(31 downto 0);
    expres4g1024m_ten_gbe1_rx_source_port: in std_logic_vector(15 downto 0);
    expres4g1024m_ten_gbe1_rx_valid: in std_logic;
    expres4g1024m_ten_gbe1_tx_ack: in std_logic;
    expres4g1024m_ten_gbe2_led_rx: in std_logic;
    expres4g1024m_ten_gbe2_led_tx: in std_logic;
    expres4g1024m_ten_gbe2_led_up: in std_logic;
    expres4g1024m_ten_gbe2_rx_data: in std_logic_vector(63 downto 0);
    expres4g1024m_ten_gbe2_rx_end_of_frame: in std_logic;
    expres4g1024m_ten_gbe2_rx_size: in std_logic_vector(15 downto 0);
    expres4g1024m_ten_gbe2_rx_source_ip: in std_logic_vector(31 downto 0);
    expres4g1024m_ten_gbe2_rx_source_port: in std_logic_vector(15 downto 0);
    expres4g1024m_ten_gbe2_rx_valid: in std_logic;
    expres4g1024m_ten_gbe2_tx_ack: in std_logic;
    expres4g1024m_vdif_framelen_w64_user_data_out: in std_logic_vector(31 downto 0);
    gateway_in: in std_logic_vector(7 downto 0);
    gateway_in1: in std_logic;
    gateway_in2: in std_logic;
    gateway_in3: in std_logic;
    gateway_in4: in std_logic_vector(15 downto 0);
    gateway_in5: in std_logic_vector(4 downto 0);
    gateway_in6: in std_logic_vector(4 downto 0);
    expres4g1024m_adc_data_i_user_data_in: out std_logic_vector(31 downto 0);
    expres4g1024m_adc_data_q_user_data_in: out std_logic_vector(31 downto 0);
    expres4g1024m_led0_gateway: out std_logic;
    expres4g1024m_led1_gateway: out std_logic;
    expres4g1024m_led2_gateway: out std_logic;
    expres4g1024m_led3_gateway: out std_logic;
    expres4g1024m_led6_gateway: out std_logic;
    expres4g1024m_led7_gateway: out std_logic;
    expres4g1024m_rtc_time_user_data_in: out std_logic_vector(31 downto 0);
    expres4g1024m_status_user_data_in: out std_logic_vector(31 downto 0);
    expres4g1024m_ten_gbe1_rst: out std_logic;
    expres4g1024m_ten_gbe1_rx_ack: out std_logic;
    expres4g1024m_ten_gbe1_tx_data: out std_logic_vector(63 downto 0);
    expres4g1024m_ten_gbe1_tx_dest_ip: out std_logic_vector(31 downto 0);
    expres4g1024m_ten_gbe1_tx_dest_port: out std_logic_vector(15 downto 0);
    expres4g1024m_ten_gbe1_tx_discard: out std_logic;
    expres4g1024m_ten_gbe1_tx_end_of_frame: out std_logic;
    expres4g1024m_ten_gbe1_tx_valid: out std_logic;
    expres4g1024m_ten_gbe2_rst: out std_logic;
    expres4g1024m_ten_gbe2_rx_ack: out std_logic;
    expres4g1024m_ten_gbe2_tx_data: out std_logic_vector(63 downto 0);
    expres4g1024m_ten_gbe2_tx_dest_ip: out std_logic_vector(31 downto 0);
    expres4g1024m_ten_gbe2_tx_dest_port: out std_logic_vector(15 downto 0);
    expres4g1024m_ten_gbe2_tx_discard: out std_logic;
    expres4g1024m_ten_gbe2_tx_end_of_frame: out std_logic;
    expres4g1024m_ten_gbe2_tx_valid: out std_logic;
    expres4g1024m_twobit_data_i_user_data_in: out std_logic_vector(31 downto 0);
    expres4g1024m_twobit_data_q_user_data_in: out std_logic_vector(31 downto 0)
  );
end expres4g1024m;

architecture structural of expres4g1024m is
  signal addsub_s_net: std_logic_vector(32 downto 0);
  signal bitreducer8to2_v10_1_samples_net: std_logic_vector(63 downto 0);
  signal bitreducer8to2_v10_1_sync_out_net: std_logic;
  signal bitreducer8to2_v10_1_syncs_out_net: std_logic_vector(7 downto 0);
  signal bitreducer8to2_v10_1_valid_out_net: std_logic;
  signal bitreducer8to2_v10_2_samples_net: std_logic_vector(63 downto 0);
  signal bitreducer8to2_v10_2_sync_out_net: std_logic;
  signal bitreducer8to2_v10_2_syncs_out_net: std_logic_vector(7 downto 0);
  signal bitreducer8to2_v10_2_valid_out_net: std_logic;
  signal bl_byte0_y_net: std_logic_vector(7 downto 0);
  signal bl_byte1_y_net: std_logic_vector(7 downto 0);
  signal bl_byte2_y_net: std_logic_vector(7 downto 0);
  signal bl_byte3_y_net: std_logic_vector(7 downto 0);
  signal ce_1_sg_x10: std_logic;
  signal clk_1_sg_x10: std_logic;
  signal concat1_y_net_x0: std_logic_vector(91 downto 0);
  signal concat1_y_net_x1: std_logic_vector(31 downto 0);
  signal concat1_y_net_x2: std_logic_vector(31 downto 0);
  signal constant1_op_net: std_logic;
  signal constant2_op_net: std_logic;
  signal constant3_op_net: std_logic_vector(9 downto 0);
  signal constant4_op_net: std_logic;
  signal constant5_op_net: std_logic;
  signal constant6_op_net: std_logic_vector(9 downto 0);
  signal constant7_op_net: std_logic;
  signal constant8_op_net: std_logic_vector(5 downto 0);
  signal constant9_op_net: std_logic_vector(5 downto 0);
  signal convert1_dout_net: std_logic;
  signal convert2_dout_net: std_logic;
  signal convert3_dout_net: std_logic;
  signal convert_dout_net: std_logic;
  signal data: std_logic_vector(63 downto 0);
  signal data_x0: std_logic_vector(63 downto 0);
  signal dly10_q_net_x0: std_logic_vector(31 downto 0);
  signal dly11_q_net_x0: std_logic;
  signal dly12_q_net: std_logic_vector(31 downto 0);
  signal dly13_q_net_x0: std_logic_vector(31 downto 0);
  signal dly14_q_net: std_logic_vector(31 downto 0);
  signal dly15_q_net: std_logic_vector(31 downto 0);
  signal dly16_q_net: std_logic_vector(31 downto 0);
  signal dly17_q_net: std_logic_vector(31 downto 0);
  signal dly18_q_net_x0: std_logic;
  signal dly19_q_net: std_logic;
  signal dly1_q_net_x0: std_logic;
  signal dly20_q_net_x0: std_logic_vector(63 downto 0);
  signal dly21_q_net_x0: std_logic;
  signal dly22_q_net_x0: std_logic;
  signal dly23_q_net_x0: std_logic;
  signal dly24_q_net_x0: std_logic_vector(31 downto 0);
  signal dly25_q_net_x0: std_logic_vector(32 downto 0);
  signal dly26_q_net_x0: std_logic;
  signal dly27_q_net_x0: std_logic_vector(31 downto 0);
  signal dly2_q_net_x0: std_logic;
  signal dly3_q_net_x0: std_logic;
  signal dly4_q_net_x0: std_logic_vector(31 downto 0);
  signal dly5_q_net_x0: std_logic_vector(31 downto 0);
  signal dly6_q_net_x0: std_logic_vector(31 downto 0);
  signal dly7_q_net_x0: std_logic_vector(91 downto 0);
  signal dly8_q_net_x0: std_logic;
  signal dly9_q_net: std_logic;
  signal dly_q_net_x0: std_logic_vector(63 downto 0);
  signal expres4g1024m_adc_data_i_user_data_in_net: std_logic_vector(31 downto 0);
  signal expres4g1024m_adc_data_q_user_data_in_net: std_logic_vector(31 downto 0);
  signal expres4g1024m_adc_user_data_valid_net: std_logic;
  signal expres4g1024m_adc_user_datai0_net: std_logic_vector(7 downto 0);
  signal expres4g1024m_adc_user_datai1_net: std_logic_vector(7 downto 0);
  signal expres4g1024m_adc_user_datai2_net: std_logic_vector(7 downto 0);
  signal expres4g1024m_adc_user_datai3_net: std_logic_vector(7 downto 0);
  signal expres4g1024m_adc_user_dataq0_net: std_logic_vector(7 downto 0);
  signal expres4g1024m_adc_user_dataq1_net: std_logic_vector(7 downto 0);
  signal expres4g1024m_adc_user_dataq2_net: std_logic_vector(7 downto 0);
  signal expres4g1024m_adc_user_dataq3_net: std_logic_vector(7 downto 0);
  signal expres4g1024m_adc_user_outofrangei0_net: std_logic;
  signal expres4g1024m_adc_user_outofrangei1_net: std_logic;
  signal expres4g1024m_adc_user_outofrangeq0_net: std_logic;
  signal expres4g1024m_adc_user_outofrangeq1_net: std_logic;
  signal expres4g1024m_adc_user_sync0_net: std_logic;
  signal expres4g1024m_adc_user_sync1_net: std_logic;
  signal expres4g1024m_adc_user_sync2_net: std_logic;
  signal expres4g1024m_adc_user_sync3_net: std_logic;
  signal expres4g1024m_bit_levels_user_data_out_net: std_logic_vector(31 downto 0);
  signal expres4g1024m_config_user_data_out_net: std_logic_vector(31 downto 0);
  signal expres4g1024m_dest_ip_user_data_out_net: std_logic_vector(31 downto 0);
  signal expres4g1024m_dest_port_offset_user_data_out_net: std_logic_vector(31 downto 0);
  signal expres4g1024m_dest_port_user_data_out_net: std_logic_vector(31 downto 0);
  signal expres4g1024m_led0_gateway_net: std_logic;
  signal expres4g1024m_led1_gateway_net: std_logic;
  signal expres4g1024m_led2_gateway_net: std_logic;
  signal expres4g1024m_led3_gateway_net: std_logic;
  signal expres4g1024m_led6_gateway_net: std_logic;
  signal expres4g1024m_led7_gateway_net: std_logic;
  signal expres4g1024m_national_semi_pll_user_data_out_net: std_logic_vector(31 downto 0);
  signal expres4g1024m_rtc_settime_user_data_out_net: std_logic_vector(31 downto 0);
  signal expres4g1024m_rtc_starttime_user_data_out_net: std_logic_vector(31 downto 0);
  signal expres4g1024m_rtc_stoptime_user_data_out_net: std_logic_vector(31 downto 0);
  signal expres4g1024m_rtc_time_user_data_in_net: std_logic_vector(31 downto 0);
  signal expres4g1024m_status_user_data_in_net: std_logic_vector(31 downto 0);
  signal expres4g1024m_ten_gbe1_led_rx_net: std_logic;
  signal expres4g1024m_ten_gbe1_led_tx_net: std_logic;
  signal expres4g1024m_ten_gbe1_led_up_net: std_logic;
  signal expres4g1024m_ten_gbe1_rst_net: std_logic;
  signal expres4g1024m_ten_gbe1_rx_ack_net: std_logic;
  signal expres4g1024m_ten_gbe1_rx_data_net: std_logic_vector(63 downto 0);
  signal expres4g1024m_ten_gbe1_rx_end_of_frame_net: std_logic;
  signal expres4g1024m_ten_gbe1_rx_size_net: std_logic_vector(15 downto 0);
  signal expres4g1024m_ten_gbe1_rx_source_ip_net: std_logic_vector(31 downto 0);
  signal expres4g1024m_ten_gbe1_rx_source_port_net: std_logic_vector(15 downto 0);
  signal expres4g1024m_ten_gbe1_rx_valid_net: std_logic;
  signal expres4g1024m_ten_gbe1_tx_ack_net: std_logic;
  signal expres4g1024m_ten_gbe1_tx_data_net: std_logic_vector(63 downto 0);
  signal expres4g1024m_ten_gbe1_tx_dest_ip_net: std_logic_vector(31 downto 0);
  signal expres4g1024m_ten_gbe1_tx_dest_port_net: std_logic_vector(15 downto 0);
  signal expres4g1024m_ten_gbe1_tx_discard_net: std_logic;
  signal expres4g1024m_ten_gbe1_tx_end_of_frame_net: std_logic;
  signal expres4g1024m_ten_gbe1_tx_valid_net: std_logic;
  signal expres4g1024m_ten_gbe2_led_rx_net: std_logic;
  signal expres4g1024m_ten_gbe2_led_tx_net: std_logic;
  signal expres4g1024m_ten_gbe2_led_up_net: std_logic;
  signal expres4g1024m_ten_gbe2_rst_net: std_logic;
  signal expres4g1024m_ten_gbe2_rx_ack_net: std_logic;
  signal expres4g1024m_ten_gbe2_rx_data_net: std_logic_vector(63 downto 0);
  signal expres4g1024m_ten_gbe2_rx_end_of_frame_net: std_logic;
  signal expres4g1024m_ten_gbe2_rx_size_net: std_logic_vector(15 downto 0);
  signal expres4g1024m_ten_gbe2_rx_source_ip_net: std_logic_vector(31 downto 0);
  signal expres4g1024m_ten_gbe2_rx_source_port_net: std_logic_vector(15 downto 0);
  signal expres4g1024m_ten_gbe2_rx_valid_net: std_logic;
  signal expres4g1024m_ten_gbe2_tx_ack_net: std_logic;
  signal expres4g1024m_ten_gbe2_tx_data_net: std_logic_vector(63 downto 0);
  signal expres4g1024m_ten_gbe2_tx_dest_ip_net: std_logic_vector(31 downto 0);
  signal expres4g1024m_ten_gbe2_tx_dest_port_net: std_logic_vector(15 downto 0);
  signal expres4g1024m_ten_gbe2_tx_discard_net: std_logic;
  signal expres4g1024m_ten_gbe2_tx_end_of_frame_net: std_logic;
  signal expres4g1024m_ten_gbe2_tx_valid_net: std_logic;
  signal expres4g1024m_twobit_data_i_user_data_in_net: std_logic_vector(31 downto 0);
  signal expres4g1024m_twobit_data_q_user_data_in_net: std_logic_vector(31 downto 0);
  signal expres4g1024m_vdif_framelen_w64_user_data_out_net: std_logic_vector(31 downto 0);
  signal gateway_in1_net: std_logic;
  signal gateway_in2_net: std_logic;
  signal gateway_in3_net: std_logic;
  signal gateway_in4_net: std_logic_vector(15 downto 0);
  signal gateway_in5_net: std_logic_vector(4 downto 0);
  signal gateway_in6_net: std_logic_vector(4 downto 0);
  signal gateway_in_net: std_logic_vector(7 downto 0);
  signal logical1_y_net_x1: std_logic;
  signal logical_y_net_x0: std_logic;
  signal lsb1_y_net: std_logic_vector(29 downto 0);
  signal register1_q_net_x0: std_logic_vector(63 downto 0);
  signal register_q_net_x0: std_logic_vector(63 downto 0);
  signal reinterpret4_output_port_net_x0: std_logic_vector(7 downto 0);
  signal reinterpret4_output_port_net_x1: std_logic_vector(7 downto 0);
  signal reinterpret5_output_port_net_x0: std_logic_vector(7 downto 0);
  signal reinterpret5_output_port_net_x1: std_logic_vector(7 downto 0);
  signal reinterpret6_output_port_net_x0: std_logic_vector(7 downto 0);
  signal reinterpret6_output_port_net_x1: std_logic_vector(7 downto 0);
  signal reinterpret7_output_port_net_x0: std_logic_vector(7 downto 0);
  signal reinterpret7_output_port_net_x1: std_logic_vector(7 downto 0);
  signal reinterpret_output_port_net_x12: std_logic_vector(7 downto 0);
  signal reinterpret_output_port_net_x13: std_logic_vector(7 downto 0);
  signal reinterpret_output_port_net_x14: std_logic_vector(7 downto 0);
  signal reinterpret_output_port_net_x15: std_logic_vector(7 downto 0);
  signal reinterpret_output_port_net_x16: std_logic_vector(7 downto 0);
  signal reinterpret_output_port_net_x17: std_logic_vector(7 downto 0);
  signal reinterpret_output_port_net_x18: std_logic_vector(7 downto 0);
  signal reinterpret_output_port_net_x19: std_logic_vector(7 downto 0);
  signal rtc32_v14_no_pps_net_x0: std_logic;
  signal rtc32_v14_pps_toggle_net_x0: std_logic;
  signal rtc32_v14_seconds_net: std_logic_vector(31 downto 0);
  signal rtc32_v14_triggered_net_x0: std_logic;
  signal simulation_multiplexer2_dout_net_x0: std_logic;
  signal simulation_multiplexer3_dout_net_x0: std_logic_vector(15 downto 0);
  signal simulation_multiplexer4_dout_net_x0: std_logic_vector(4 downto 0);
  signal simulation_multiplexer5_dout_net_x0: std_logic_vector(4 downto 0);
  signal simulation_multiplexer_dout_net_x0: std_logic;
  signal sl_10lsb1_y_net: std_logic_vector(9 downto 0);
  signal sl_10lsb_y_net: std_logic_vector(9 downto 0);
  signal vdif_packetizer_v15_2_dbg_dw64counter_net: std_logic_vector(9 downto 0);
  signal vdif_packetizer_v15_2_dbg_fifo_empty_net: std_logic;
  signal vdif_packetizer_v15_2_tx_discard_net: std_logic;
  signal vdif_packetizer_v15_2_tx_end_of_frame_net: std_logic;
  signal vdif_packetizer_v15_2_tx_valid_net: std_logic;
  signal vdif_packetizer_v15_dbg_dw64counter_net: std_logic_vector(9 downto 0);
  signal vdif_packetizer_v15_dbg_fifo_empty_net: std_logic;
  signal vdif_packetizer_v15_tx_discard_net: std_logic;
  signal vdif_packetizer_v15_tx_end_of_frame_net: std_logic;
  signal vdif_packetizer_v15_tx_valid_net: std_logic;

begin
  ce_1_sg_x10 <= ce_1;
  clk_1_sg_x10 <= clk_1;
  expres4g1024m_adc_user_data_valid_net <= expres4g1024m_adc_user_data_valid;
  expres4g1024m_adc_user_datai0_net <= expres4g1024m_adc_user_datai0;
  expres4g1024m_adc_user_datai1_net <= expres4g1024m_adc_user_datai1;
  expres4g1024m_adc_user_datai2_net <= expres4g1024m_adc_user_datai2;
  expres4g1024m_adc_user_datai3_net <= expres4g1024m_adc_user_datai3;
  expres4g1024m_adc_user_dataq0_net <= expres4g1024m_adc_user_dataq0;
  expres4g1024m_adc_user_dataq1_net <= expres4g1024m_adc_user_dataq1;
  expres4g1024m_adc_user_dataq2_net <= expres4g1024m_adc_user_dataq2;
  expres4g1024m_adc_user_dataq3_net <= expres4g1024m_adc_user_dataq3;
  expres4g1024m_adc_user_outofrangei0_net <= expres4g1024m_adc_user_outofrangei0;
  expres4g1024m_adc_user_outofrangei1_net <= expres4g1024m_adc_user_outofrangei1;
  expres4g1024m_adc_user_outofrangeq0_net <= expres4g1024m_adc_user_outofrangeq0;
  expres4g1024m_adc_user_outofrangeq1_net <= expres4g1024m_adc_user_outofrangeq1;
  expres4g1024m_adc_user_sync0_net <= expres4g1024m_adc_user_sync0;
  expres4g1024m_adc_user_sync1_net <= expres4g1024m_adc_user_sync1;
  expres4g1024m_adc_user_sync2_net <= expres4g1024m_adc_user_sync2;
  expres4g1024m_adc_user_sync3_net <= expres4g1024m_adc_user_sync3;
  expres4g1024m_bit_levels_user_data_out_net <= expres4g1024m_bit_levels_user_data_out;
  expres4g1024m_config_user_data_out_net <= expres4g1024m_config_user_data_out;
  expres4g1024m_dest_ip_user_data_out_net <= expres4g1024m_dest_ip_user_data_out;
  expres4g1024m_dest_port_offset_user_data_out_net <= expres4g1024m_dest_port_offset_user_data_out;
  expres4g1024m_dest_port_user_data_out_net <= expres4g1024m_dest_port_user_data_out;
  expres4g1024m_national_semi_pll_user_data_out_net <= expres4g1024m_national_semi_pll_user_data_out;
  expres4g1024m_rtc_settime_user_data_out_net <= expres4g1024m_rtc_settime_user_data_out;
  expres4g1024m_rtc_starttime_user_data_out_net <= expres4g1024m_rtc_starttime_user_data_out;
  expres4g1024m_rtc_stoptime_user_data_out_net <= expres4g1024m_rtc_stoptime_user_data_out;
  expres4g1024m_ten_gbe1_led_rx_net <= expres4g1024m_ten_gbe1_led_rx;
  expres4g1024m_ten_gbe1_led_tx_net <= expres4g1024m_ten_gbe1_led_tx;
  expres4g1024m_ten_gbe1_led_up_net <= expres4g1024m_ten_gbe1_led_up;
  expres4g1024m_ten_gbe1_rx_data_net <= expres4g1024m_ten_gbe1_rx_data;
  expres4g1024m_ten_gbe1_rx_end_of_frame_net <= expres4g1024m_ten_gbe1_rx_end_of_frame;
  expres4g1024m_ten_gbe1_rx_size_net <= expres4g1024m_ten_gbe1_rx_size;
  expres4g1024m_ten_gbe1_rx_source_ip_net <= expres4g1024m_ten_gbe1_rx_source_ip;
  expres4g1024m_ten_gbe1_rx_source_port_net <= expres4g1024m_ten_gbe1_rx_source_port;
  expres4g1024m_ten_gbe1_rx_valid_net <= expres4g1024m_ten_gbe1_rx_valid;
  expres4g1024m_ten_gbe1_tx_ack_net <= expres4g1024m_ten_gbe1_tx_ack;
  expres4g1024m_ten_gbe2_led_rx_net <= expres4g1024m_ten_gbe2_led_rx;
  expres4g1024m_ten_gbe2_led_tx_net <= expres4g1024m_ten_gbe2_led_tx;
  expres4g1024m_ten_gbe2_led_up_net <= expres4g1024m_ten_gbe2_led_up;
  expres4g1024m_ten_gbe2_rx_data_net <= expres4g1024m_ten_gbe2_rx_data;
  expres4g1024m_ten_gbe2_rx_end_of_frame_net <= expres4g1024m_ten_gbe2_rx_end_of_frame;
  expres4g1024m_ten_gbe2_rx_size_net <= expres4g1024m_ten_gbe2_rx_size;
  expres4g1024m_ten_gbe2_rx_source_ip_net <= expres4g1024m_ten_gbe2_rx_source_ip;
  expres4g1024m_ten_gbe2_rx_source_port_net <= expres4g1024m_ten_gbe2_rx_source_port;
  expres4g1024m_ten_gbe2_rx_valid_net <= expres4g1024m_ten_gbe2_rx_valid;
  expres4g1024m_ten_gbe2_tx_ack_net <= expres4g1024m_ten_gbe2_tx_ack;
  expres4g1024m_vdif_framelen_w64_user_data_out_net <= expres4g1024m_vdif_framelen_w64_user_data_out;
  gateway_in_net <= gateway_in;
  gateway_in1_net <= gateway_in1;
  gateway_in2_net <= gateway_in2;
  gateway_in3_net <= gateway_in3;
  gateway_in4_net <= gateway_in4;
  gateway_in5_net <= gateway_in5;
  gateway_in6_net <= gateway_in6;
  expres4g1024m_adc_data_i_user_data_in <= expres4g1024m_adc_data_i_user_data_in_net;
  expres4g1024m_adc_data_q_user_data_in <= expres4g1024m_adc_data_q_user_data_in_net;
  expres4g1024m_led0_gateway <= expres4g1024m_led0_gateway_net;
  expres4g1024m_led1_gateway <= expres4g1024m_led1_gateway_net;
  expres4g1024m_led2_gateway <= expres4g1024m_led2_gateway_net;
  expres4g1024m_led3_gateway <= expres4g1024m_led3_gateway_net;
  expres4g1024m_led6_gateway <= expres4g1024m_led6_gateway_net;
  expres4g1024m_led7_gateway <= expres4g1024m_led7_gateway_net;
  expres4g1024m_rtc_time_user_data_in <= expres4g1024m_rtc_time_user_data_in_net;
  expres4g1024m_status_user_data_in <= expres4g1024m_status_user_data_in_net;
  expres4g1024m_ten_gbe1_rst <= expres4g1024m_ten_gbe1_rst_net;
  expres4g1024m_ten_gbe1_rx_ack <= expres4g1024m_ten_gbe1_rx_ack_net;
  expres4g1024m_ten_gbe1_tx_data <= expres4g1024m_ten_gbe1_tx_data_net;
  expres4g1024m_ten_gbe1_tx_dest_ip <= expres4g1024m_ten_gbe1_tx_dest_ip_net;
  expres4g1024m_ten_gbe1_tx_dest_port <= expres4g1024m_ten_gbe1_tx_dest_port_net;
  expres4g1024m_ten_gbe1_tx_discard <= expres4g1024m_ten_gbe1_tx_discard_net;
  expres4g1024m_ten_gbe1_tx_end_of_frame <= expres4g1024m_ten_gbe1_tx_end_of_frame_net;
  expres4g1024m_ten_gbe1_tx_valid <= expres4g1024m_ten_gbe1_tx_valid_net;
  expres4g1024m_ten_gbe2_rst <= expres4g1024m_ten_gbe2_rst_net;
  expres4g1024m_ten_gbe2_rx_ack <= expres4g1024m_ten_gbe2_rx_ack_net;
  expres4g1024m_ten_gbe2_tx_data <= expres4g1024m_ten_gbe2_tx_data_net;
  expres4g1024m_ten_gbe2_tx_dest_ip <= expres4g1024m_ten_gbe2_tx_dest_ip_net;
  expres4g1024m_ten_gbe2_tx_dest_port <= expres4g1024m_ten_gbe2_tx_dest_port_net;
  expres4g1024m_ten_gbe2_tx_discard <= expres4g1024m_ten_gbe2_tx_discard_net;
  expres4g1024m_ten_gbe2_tx_end_of_frame <= expres4g1024m_ten_gbe2_tx_end_of_frame_net;
  expres4g1024m_ten_gbe2_tx_valid <= expres4g1024m_ten_gbe2_tx_valid_net;
  expres4g1024m_twobit_data_i_user_data_in <= expres4g1024m_twobit_data_i_user_data_in_net;
  expres4g1024m_twobit_data_q_user_data_in <= expres4g1024m_twobit_data_q_user_data_in_net;

  adc_9852d04a8e: entity work.adc_entity_9852d04a8e
    port map (
      ce_1 => ce_1_sg_x10,
      clk_1 => clk_1_sg_x10,
      expres4g1024m_adc_user_datai0 => expres4g1024m_adc_user_datai0_net,
      expres4g1024m_adc_user_datai1 => expres4g1024m_adc_user_datai1_net,
      expres4g1024m_adc_user_datai2 => expres4g1024m_adc_user_datai2_net,
      expres4g1024m_adc_user_datai3 => expres4g1024m_adc_user_datai3_net,
      expres4g1024m_adc_user_dataq0 => expres4g1024m_adc_user_dataq0_net,
      expres4g1024m_adc_user_dataq1 => expres4g1024m_adc_user_dataq1_net,
      expres4g1024m_adc_user_dataq2 => expres4g1024m_adc_user_dataq2_net,
      expres4g1024m_adc_user_dataq3 => expres4g1024m_adc_user_dataq3_net,
      i0 => reinterpret_output_port_net_x12,
      i1 => reinterpret_output_port_net_x13,
      i2 => reinterpret_output_port_net_x14,
      i3 => reinterpret_output_port_net_x15,
      q0 => reinterpret_output_port_net_x16,
      q1 => reinterpret_output_port_net_x17,
      q2 => reinterpret_output_port_net_x18,
      q3 => reinterpret_output_port_net_x19
    );

  adc_data_i_a3a8938725: entity work.adc_data_i_entity_a3a8938725
    port map (
      reg_out => dly13_q_net_x0,
      convert_x0 => expres4g1024m_adc_data_i_user_data_in_net
    );

  adc_data_q_64b50d7ffe: entity work.adc_data_q_entity_64b50d7ffe
    port map (
      reg_out => dly27_q_net_x0,
      convert_x0 => expres4g1024m_adc_data_q_user_data_in_net
    );

  adccat1_e02ada5f8a: entity work.adccat1_entity_e02ada5f8a
    port map (
      iq0 => reinterpret_output_port_net_x12,
      iq1 => reinterpret_output_port_net_x13,
      iq2 => reinterpret_output_port_net_x14,
      iq3 => reinterpret_output_port_net_x15,
      cat => concat1_y_net_x1
    );

  adccat2_ceac40d612: entity work.adccat2_entity_ceac40d612
    port map (
      iq0 => reinterpret_output_port_net_x16,
      iq1 => reinterpret_output_port_net_x17,
      iq2 => reinterpret_output_port_net_x18,
      iq3 => reinterpret_output_port_net_x19,
      cat => concat1_y_net_x2
    );

  adcuncat1_eb19c49dca: entity work.adcuncat1_entity_eb19c49dca
    port map (
      concat => concat1_y_net_x2,
      iq0 => reinterpret4_output_port_net_x0,
      iq1 => reinterpret5_output_port_net_x0,
      iq2 => reinterpret6_output_port_net_x0,
      iq3 => reinterpret7_output_port_net_x0
    );

  adcuncat2_4514881654: entity work.adcuncat2_entity_4514881654
    port map (
      concat => concat1_y_net_x1,
      iq0 => reinterpret4_output_port_net_x1,
      iq1 => reinterpret5_output_port_net_x1,
      iq2 => reinterpret6_output_port_net_x1,
      iq3 => reinterpret7_output_port_net_x1
    );

  addsub: entity work.xladdsub
    generic map (
      a_arith => xlUnsigned,
      a_bin_pt => 0,
      a_width => 32,
      b_arith => xlUnsigned,
      b_bin_pt => 0,
      b_width => 32,
      c_has_b_out => 0,
      c_has_c_out => 0,
      c_has_q => 1,
      c_has_q_b_out => 0,
      c_has_q_c_out => 0,
      c_has_s => 0,
      c_latency => 1,
      c_output_width => 33,
      core_name0 => "adder_subtracter_virtex2p_7_0_23d84c584623d65e",
      extra_registers => 0,
      full_s_arith => 1,
      full_s_width => 33,
      latency => 1,
      mode => 1,
      overflow => 1,
      quantization => 1,
      s_arith => xlUnsigned,
      s_bin_pt => 0,
      s_width => 33
    )
    port map (
      a => expres4g1024m_dest_port_user_data_out_net,
      b => expres4g1024m_dest_port_offset_user_data_out_net,
      ce => ce_1_sg_x10,
      clk => clk_1_sg_x10,
      clr => '0',
      en => "1",
      s => addsub_s_net
    );

  assemblestatus_7fd680fdc6: entity work.assemblestatus_entity_7fd680fdc6
    port map (
      adcvalid => expres4g1024m_adc_user_data_valid_net,
      onepps => logical1_y_net_x1,
      oneppsfault => rtc32_v14_no_pps_net_x0,
      rtctoggled => rtc32_v14_pps_toggle_net_x0,
      rtctriggered => rtc32_v14_triggered_net_x0,
      status => concat1_y_net_x0
    );

  bitreducer8to2_v10_1: entity work.bitreducer8to2_v10
    port map (
      ce => ce_1_sg_x10,
      clk => clk_1_sg_x10,
      magnitude_level_neg => bl_byte1_y_net,
      magnitude_level_pos => bl_byte0_y_net,
      rst => simulation_multiplexer2_dout_net_x0,
      s0 => reinterpret4_output_port_net_x1,
      s1 => reinterpret5_output_port_net_x1,
      s2 => reinterpret6_output_port_net_x1,
      s3 => reinterpret7_output_port_net_x1,
      sync_in => logical1_y_net_x1,
      valid_in => expres4g1024m_adc_user_data_valid_net,
      samples => bitreducer8to2_v10_1_samples_net,
      sync_out => bitreducer8to2_v10_1_sync_out_net,
      syncs_out => bitreducer8to2_v10_1_syncs_out_net,
      valid_out => bitreducer8to2_v10_1_valid_out_net
    );

  bitreducer8to2_v10_2: entity work.bitreducer8to2_v10
    port map (
      ce => ce_1_sg_x10,
      clk => clk_1_sg_x10,
      magnitude_level_neg => bl_byte3_y_net,
      magnitude_level_pos => bl_byte2_y_net,
      rst => simulation_multiplexer2_dout_net_x0,
      s0 => reinterpret4_output_port_net_x0,
      s1 => reinterpret5_output_port_net_x0,
      s2 => reinterpret6_output_port_net_x0,
      s3 => reinterpret7_output_port_net_x0,
      sync_in => logical1_y_net_x1,
      valid_in => expres4g1024m_adc_user_data_valid_net,
      samples => bitreducer8to2_v10_2_samples_net,
      sync_out => bitreducer8to2_v10_2_sync_out_net,
      syncs_out => bitreducer8to2_v10_2_syncs_out_net,
      valid_out => bitreducer8to2_v10_2_valid_out_net
    );

  bl_byte0: entity work.bl_byte0_85614cf66d
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      x => dly14_q_net,
      y => bl_byte0_y_net
    );

  bl_byte1: entity work.bl_byte1_4dee1560eb
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      x => dly14_q_net,
      y => bl_byte1_y_net
    );

  bl_byte2: entity work.bl_byte2_87e71d2c59
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      x => dly14_q_net,
      y => bl_byte2_y_net
    );

  bl_byte3: entity work.bl_byte3_62ea3ff720
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      x => dly14_q_net,
      y => bl_byte3_y_net
    );

  configsys_72b77062d8: entity work.configsys_entity_72b77062d8
    port map (
      configreg => dly6_q_net_x0,
      bitspersample => simulation_multiplexer4_dout_net_x0,
      log2channels => simulation_multiplexer5_dout_net_x0,
      reloadrtc => simulation_multiplexer_dout_net_x0,
      stationid => simulation_multiplexer3_dout_net_x0,
      sysreset => simulation_multiplexer2_dout_net_x0
    );

  constant1: entity work.constant1_2ba2b4f03c
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      op(0) => constant1_op_net
    );

  constant2: entity work.constant2_a7a5800303
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      op(0) => constant2_op_net
    );

  constant3: entity work.constant3_2994ece7ca
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      op => constant3_op_net
    );

  constant4: entity work.constant4_ad9ae8727a
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      op(0) => constant4_op_net
    );

  constant5: entity work.constant5_f77e6e4b80
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      op(0) => constant5_op_net
    );

  constant6: entity work.constant6_4c5259419a
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      op => constant6_op_net
    );

  constant7: entity work.constant7_5a759dc8e0
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      op(0) => constant7_op_net
    );

  constant8: entity work.constant8_738ac8f738
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      op => constant8_op_net
    );

  constant9: entity work.constant9_7040000009
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      op => constant9_op_net
    );

  convert: entity work.xlconvert
    generic map (
      bool_conversion => 1,
      din_arith => 1,
      din_bin_pt => 0,
      din_width => 1,
      dout_arith => 1,
      dout_bin_pt => 0,
      dout_width => 1,
      latency => 0,
      overflow => xlWrap,
      quantization => xlTruncate
    )
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      din(0) => vdif_packetizer_v15_tx_valid_net,
      dout(0) => convert_dout_net
    );

  convert1: entity work.xlconvert
    generic map (
      bool_conversion => 1,
      din_arith => 1,
      din_bin_pt => 0,
      din_width => 1,
      dout_arith => 1,
      dout_bin_pt => 0,
      dout_width => 1,
      latency => 0,
      overflow => xlWrap,
      quantization => xlTruncate
    )
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      din(0) => vdif_packetizer_v15_2_tx_valid_net,
      dout(0) => convert1_dout_net
    );

  convert2: entity work.xlconvert
    generic map (
      bool_conversion => 1,
      din_arith => 1,
      din_bin_pt => 0,
      din_width => 1,
      dout_arith => 1,
      dout_bin_pt => 0,
      dout_width => 1,
      latency => 0,
      overflow => xlWrap,
      quantization => xlTruncate
    )
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      din(0) => bitreducer8to2_v10_1_valid_out_net,
      dout(0) => convert2_dout_net
    );

  convert3: entity work.xlconvert
    generic map (
      bool_conversion => 1,
      din_arith => 1,
      din_bin_pt => 0,
      din_width => 1,
      dout_arith => 1,
      dout_bin_pt => 0,
      dout_width => 1,
      latency => 0,
      overflow => xlWrap,
      quantization => xlTruncate
    )
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      din(0) => bitreducer8to2_v10_2_valid_out_net,
      dout(0) => convert3_dout_net
    );

  dly: entity work.xldelay
    generic map (
      latency => 16,
      reg_retiming => 0,
      width => 64
    )
    port map (
      ce => ce_1_sg_x10,
      clk => clk_1_sg_x10,
      d => data,
      en => '1',
      q => dly_q_net_x0
    );

  dly1: entity work.xldelay
    generic map (
      latency => 16,
      reg_retiming => 0,
      width => 1
    )
    port map (
      ce => ce_1_sg_x10,
      clk => clk_1_sg_x10,
      d(0) => convert_dout_net,
      en => '1',
      q(0) => dly1_q_net_x0
    );

  dly10: entity work.xldelay
    generic map (
      latency => 4,
      reg_retiming => 0,
      width => 32
    )
    port map (
      ce => ce_1_sg_x10,
      clk => clk_1_sg_x10,
      d => rtc32_v14_seconds_net,
      en => '1',
      q => dly10_q_net_x0
    );

  dly11: entity work.xldelay
    generic map (
      latency => 4,
      reg_retiming => 0,
      width => 1
    )
    port map (
      ce => ce_1_sg_x10,
      clk => clk_1_sg_x10,
      d(0) => rtc32_v14_no_pps_net_x0,
      en => '1',
      q(0) => dly11_q_net_x0
    );

  dly12: entity work.xldelay
    generic map (
      latency => 4,
      reg_retiming => 0,
      width => 32
    )
    port map (
      ce => ce_1_sg_x10,
      clk => clk_1_sg_x10,
      d => expres4g1024m_vdif_framelen_w64_user_data_out_net,
      en => '1',
      q => dly12_q_net
    );

  dly13: entity work.xldelay
    generic map (
      latency => 4,
      reg_retiming => 0,
      width => 32
    )
    port map (
      ce => ce_1_sg_x10,
      clk => clk_1_sg_x10,
      d => concat1_y_net_x1,
      en => '1',
      q => dly13_q_net_x0
    );

  dly14: entity work.xldelay
    generic map (
      latency => 4,
      reg_retiming => 0,
      width => 32
    )
    port map (
      ce => ce_1_sg_x10,
      clk => clk_1_sg_x10,
      d => expres4g1024m_bit_levels_user_data_out_net,
      en => '1',
      q => dly14_q_net
    );

  dly15: entity work.xldelay
    generic map (
      latency => 4,
      reg_retiming => 0,
      width => 32
    )
    port map (
      ce => ce_1_sg_x10,
      clk => clk_1_sg_x10,
      d => expres4g1024m_rtc_starttime_user_data_out_net,
      en => '1',
      q => dly15_q_net
    );

  dly16: entity work.xldelay
    generic map (
      latency => 4,
      reg_retiming => 0,
      width => 32
    )
    port map (
      ce => ce_1_sg_x10,
      clk => clk_1_sg_x10,
      d => expres4g1024m_rtc_stoptime_user_data_out_net,
      en => '1',
      q => dly16_q_net
    );

  dly17: entity work.xldelay
    generic map (
      latency => 4,
      reg_retiming => 0,
      width => 32
    )
    port map (
      ce => ce_1_sg_x10,
      clk => clk_1_sg_x10,
      d => expres4g1024m_rtc_settime_user_data_out_net,
      en => '1',
      q => dly17_q_net
    );

  dly18: entity work.xldelay
    generic map (
      latency => 4,
      reg_retiming => 0,
      width => 1
    )
    port map (
      ce => ce_1_sg_x10,
      clk => clk_1_sg_x10,
      d(0) => rtc32_v14_pps_toggle_net_x0,
      en => '1',
      q(0) => dly18_q_net_x0
    );

  dly19: entity work.xldelay
    generic map (
      latency => 16,
      reg_retiming => 0,
      width => 1
    )
    port map (
      ce => ce_1_sg_x10,
      clk => clk_1_sg_x10,
      d(0) => simulation_multiplexer2_dout_net_x0,
      en => '1',
      q(0) => dly19_q_net
    );

  dly2: entity work.xldelay
    generic map (
      latency => 16,
      reg_retiming => 0,
      width => 1
    )
    port map (
      ce => ce_1_sg_x10,
      clk => clk_1_sg_x10,
      d(0) => vdif_packetizer_v15_tx_end_of_frame_net,
      en => '1',
      q(0) => dly2_q_net_x0
    );

  dly20: entity work.xldelay
    generic map (
      latency => 16,
      reg_retiming => 0,
      width => 64
    )
    port map (
      ce => ce_1_sg_x10,
      clk => clk_1_sg_x10,
      d => data_x0,
      en => '1',
      q => dly20_q_net_x0
    );

  dly21: entity work.xldelay
    generic map (
      latency => 16,
      reg_retiming => 0,
      width => 1
    )
    port map (
      ce => ce_1_sg_x10,
      clk => clk_1_sg_x10,
      d(0) => convert1_dout_net,
      en => '1',
      q(0) => dly21_q_net_x0
    );

  dly22: entity work.xldelay
    generic map (
      latency => 16,
      reg_retiming => 0,
      width => 1
    )
    port map (
      ce => ce_1_sg_x10,
      clk => clk_1_sg_x10,
      d(0) => vdif_packetizer_v15_2_tx_end_of_frame_net,
      en => '1',
      q(0) => dly22_q_net_x0
    );

  dly23: entity work.xldelay
    generic map (
      latency => 16,
      reg_retiming => 0,
      width => 1
    )
    port map (
      ce => ce_1_sg_x10,
      clk => clk_1_sg_x10,
      d(0) => vdif_packetizer_v15_2_tx_discard_net,
      en => '1',
      q(0) => dly23_q_net_x0
    );

  dly24: entity work.xldelay
    generic map (
      latency => 16,
      reg_retiming => 0,
      width => 32
    )
    port map (
      ce => ce_1_sg_x10,
      clk => clk_1_sg_x10,
      d => expres4g1024m_dest_ip_user_data_out_net,
      en => '1',
      q => dly24_q_net_x0
    );

  dly25: entity work.xldelay
    generic map (
      latency => 16,
      reg_retiming => 0,
      width => 33
    )
    port map (
      ce => ce_1_sg_x10,
      clk => clk_1_sg_x10,
      d => addsub_s_net,
      en => '1',
      q => dly25_q_net_x0
    );

  dly26: entity work.xldelay
    generic map (
      latency => 16,
      reg_retiming => 0,
      width => 1
    )
    port map (
      ce => ce_1_sg_x10,
      clk => clk_1_sg_x10,
      d(0) => simulation_multiplexer2_dout_net_x0,
      en => '1',
      q(0) => dly26_q_net_x0
    );

  dly27: entity work.xldelay
    generic map (
      latency => 4,
      reg_retiming => 0,
      width => 32
    )
    port map (
      ce => ce_1_sg_x10,
      clk => clk_1_sg_x10,
      d => concat1_y_net_x2,
      en => '1',
      q => dly27_q_net_x0
    );

  dly3: entity work.xldelay
    generic map (
      latency => 16,
      reg_retiming => 0,
      width => 1
    )
    port map (
      ce => ce_1_sg_x10,
      clk => clk_1_sg_x10,
      d(0) => vdif_packetizer_v15_tx_discard_net,
      en => '1',
      q(0) => dly3_q_net_x0
    );

  dly4: entity work.xldelay
    generic map (
      latency => 16,
      reg_retiming => 0,
      width => 32
    )
    port map (
      ce => ce_1_sg_x10,
      clk => clk_1_sg_x10,
      d => expres4g1024m_dest_ip_user_data_out_net,
      en => '1',
      q => dly4_q_net_x0
    );

  dly5: entity work.xldelay
    generic map (
      latency => 16,
      reg_retiming => 0,
      width => 32
    )
    port map (
      ce => ce_1_sg_x10,
      clk => clk_1_sg_x10,
      d => expres4g1024m_dest_port_user_data_out_net,
      en => '1',
      q => dly5_q_net_x0
    );

  dly6: entity work.xldelay
    generic map (
      latency => 4,
      reg_retiming => 0,
      width => 32
    )
    port map (
      ce => ce_1_sg_x10,
      clk => clk_1_sg_x10,
      d => expres4g1024m_config_user_data_out_net,
      en => '1',
      q => dly6_q_net_x0
    );

  dly7: entity work.xldelay
    generic map (
      latency => 4,
      reg_retiming => 0,
      width => 92
    )
    port map (
      ce => ce_1_sg_x10,
      clk => clk_1_sg_x10,
      d => concat1_y_net_x0,
      en => '1',
      q => dly7_q_net_x0
    );

  dly8: entity work.xldelay
    generic map (
      latency => 16,
      reg_retiming => 0,
      width => 1
    )
    port map (
      ce => ce_1_sg_x10,
      clk => clk_1_sg_x10,
      d(0) => simulation_multiplexer2_dout_net_x0,
      en => '1',
      q(0) => dly8_q_net_x0
    );

  dly9: entity work.xldelay
    generic map (
      latency => 16,
      reg_retiming => 0,
      width => 1
    )
    port map (
      ce => ce_1_sg_x10,
      clk => clk_1_sg_x10,
      d(0) => simulation_multiplexer2_dout_net_x0,
      en => '1',
      q(0) => dly9_q_net
    );

  led0_adcb04e180: entity work.led0_entity_adcb04e180
    port map (
      gpio_out => expres4g1024m_ten_gbe2_led_rx_net,
      convert_x0 => expres4g1024m_led0_gateway_net
    );

  led1_6df427b2a9: entity work.led1_entity_6df427b2a9
    port map (
      gpio_out => expres4g1024m_ten_gbe2_led_tx_net,
      convert_x0 => expres4g1024m_led1_gateway_net
    );

  led2_a89ed2d92f: entity work.led2_entity_a89ed2d92f
    port map (
      gpio_out => expres4g1024m_ten_gbe1_led_rx_net,
      convert_x0 => expres4g1024m_led2_gateway_net
    );

  led3_de4918e802: entity work.led3_entity_de4918e802
    port map (
      gpio_out => expres4g1024m_ten_gbe1_led_tx_net,
      convert_x0 => expres4g1024m_led3_gateway_net
    );

  led6_89f383e74d: entity work.led6_entity_89f383e74d
    port map (
      gpio_out => dly11_q_net_x0,
      convert_x0 => expres4g1024m_led6_gateway_net
    );

  led7_fc9cf74af9: entity work.led7_entity_fc9cf74af9
    port map (
      gpio_out => dly18_q_net_x0,
      convert_x0 => expres4g1024m_led7_gateway_net
    );

  logical: entity work.logical_093b0449cf
    port map (
      ce => ce_1_sg_x10,
      clk => clk_1_sg_x10,
      clr => '0',
      d0(0) => expres4g1024m_adc_user_sync0_net,
      d1(0) => expres4g1024m_adc_user_sync1_net,
      d2(0) => expres4g1024m_adc_user_sync2_net,
      d3(0) => expres4g1024m_adc_user_sync3_net,
      y(0) => logical_y_net_x0
    );

  lsb1: entity work.lsb1_618afcaae2
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      x => rtc32_v14_seconds_net,
      y => lsb1_y_net
    );

  posedge_aac04e502a: entity work.posedge_entity_aac04e502a
    port map (
      ce_1 => ce_1_sg_x10,
      clk_1 => clk_1_sg_x10,
      in1 => logical_y_net_x0,
      out1 => logical1_y_net_x1
    );

  register1: entity work.xlregister
    generic map (
      d_width => 64,
      init_value => b"0000000000000000000000000000000000000000000000000000000000000000"
    )
    port map (
      ce => ce_1_sg_x10,
      clk => clk_1_sg_x10,
      d => bitreducer8to2_v10_2_samples_net,
      en(0) => convert3_dout_net,
      rst => "0",
      q => register1_q_net_x0
    );

  register_x0: entity work.xlregister
    generic map (
      d_width => 64,
      init_value => b"0000000000000000000000000000000000000000000000000000000000000000"
    )
    port map (
      ce => ce_1_sg_x10,
      clk => clk_1_sg_x10,
      d => bitreducer8to2_v10_1_samples_net,
      en(0) => convert2_dout_net,
      rst => "0",
      q => register_q_net_x0
    );

  rtc32_v14_x0: entity work.rtc32_v14
    generic map (
      SYS_FREQ_HZ => 256000000
    )
    port map (
      ce => ce_1_sg_x10,
      clk => clk_1_sg_x10,
      one_pps => bitreducer8to2_v10_1_sync_out_net,
      rst => simulation_multiplexer2_dout_net_x0,
      systick => constant2_op_net,
      time_reload => simulation_multiplexer_dout_net_x0,
      time_set => dly17_q_net,
      time_trigstart => dly15_q_net,
      time_trigstop => dly16_q_net,
      no_pps => rtc32_v14_no_pps_net_x0,
      pps_toggle => rtc32_v14_pps_toggle_net_x0,
      seconds => rtc32_v14_seconds_net,
      triggered => rtc32_v14_triggered_net_x0
    );

  rtc_time_e8033653dc: entity work.rtc_time_entity_e8033653dc
    port map (
      reg_out => dly10_q_net_x0,
      convert_x0 => expres4g1024m_rtc_time_user_data_in_net
    );

  sl_10lsb: entity work.sl_10lsb_4817575a2c
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      x => dly12_q_net,
      y => sl_10lsb_y_net
    );

  sl_10lsb1: entity work.sl_10lsb1_e3e25df95e
    port map (
      ce => '0',
      clk => '0',
      clr => '0',
      x => dly12_q_net,
      y => sl_10lsb1_y_net
    );

  status_c438123aa7: entity work.status_entity_c438123aa7
    port map (
      reg_out => dly7_q_net_x0,
      convert_x0 => expres4g1024m_status_user_data_in_net
    );

  ten_gbe1_b0a1ef16c5: entity work.ten_gbe1_entity_b0a1ef16c5
    port map (
      rst => dly26_q_net_x0,
      rx_ack => expres4g1024m_ten_gbe1_rx_valid_net,
      tx_data => dly20_q_net_x0,
      tx_dest_ip => dly24_q_net_x0,
      tx_dest_port => dly25_q_net_x0,
      tx_discard => dly23_q_net_x0,
      tx_end_of_frame => dly22_q_net_x0,
      tx_valid => dly21_q_net_x0,
      convert_rst_x0 => expres4g1024m_ten_gbe1_rst_net,
      convert_rx_ack_x0 => expres4g1024m_ten_gbe1_rx_ack_net,
      convert_tx_data_x0 => expres4g1024m_ten_gbe1_tx_data_net,
      convert_tx_dest_ip_x0 => expres4g1024m_ten_gbe1_tx_dest_ip_net,
      convert_tx_discard_x0 => expres4g1024m_ten_gbe1_tx_discard_net,
      convert_tx_end_of_frame_x0 => expres4g1024m_ten_gbe1_tx_end_of_frame_net,
      convert_tx_port_x0 => expres4g1024m_ten_gbe1_tx_dest_port_net,
      convert_tx_valid_x0 => expres4g1024m_ten_gbe1_tx_valid_net
    );

  ten_gbe2_ddd9f696b9: entity work.ten_gbe2_entity_ddd9f696b9
    port map (
      rst => dly8_q_net_x0,
      rx_ack => expres4g1024m_ten_gbe2_rx_valid_net,
      tx_data => dly_q_net_x0,
      tx_dest_ip => dly4_q_net_x0,
      tx_dest_port => dly5_q_net_x0,
      tx_discard => dly3_q_net_x0,
      tx_end_of_frame => dly2_q_net_x0,
      tx_valid => dly1_q_net_x0,
      convert_rst_x0 => expres4g1024m_ten_gbe2_rst_net,
      convert_rx_ack_x0 => expres4g1024m_ten_gbe2_rx_ack_net,
      convert_tx_data_x0 => expres4g1024m_ten_gbe2_tx_data_net,
      convert_tx_dest_ip_x0 => expres4g1024m_ten_gbe2_tx_dest_ip_net,
      convert_tx_discard_x0 => expres4g1024m_ten_gbe2_tx_discard_net,
      convert_tx_end_of_frame_x0 => expres4g1024m_ten_gbe2_tx_end_of_frame_net,
      convert_tx_port_x0 => expres4g1024m_ten_gbe2_tx_dest_port_net,
      convert_tx_valid_x0 => expres4g1024m_ten_gbe2_tx_valid_net
    );

  twobit_data_i_0b92d44297: entity work.twobit_data_i_entity_0b92d44297
    port map (
      reg_out => register_q_net_x0,
      convert_x0 => expres4g1024m_twobit_data_i_user_data_in_net
    );

  twobit_data_q_b7296da730: entity work.twobit_data_q_entity_b7296da730
    port map (
      reg_out => register1_q_net_x0,
      convert_x0 => expres4g1024m_twobit_data_q_user_data_in_net
    );

  vdif_packetizer_v15_2: entity work.vdif_packetizer_v15
    generic map (
      frameCountLimit => 67108864,
      frameLenLimit => 4096
    )
    port map (
      bitspersample => simulation_multiplexer4_dout_net_x0,
      ce => ce_1_sg_x10,
      clk => clk_1_sg_x10,
      complex => constant5_op_net,
      data_in => bitreducer8to2_v10_2_samples_net,
      data_valid => bitreducer8to2_v10_2_valid_out_net,
      dw64_per_frame => sl_10lsb1_y_net,
      enable => constant7_op_net,
      epoch => constant9_op_net,
      epseconds => lsb1_y_net,
      log2channels => simulation_multiplexer5_dout_net_x0,
      rst => dly19_q_net,
      station_id => simulation_multiplexer3_dout_net_x0,
      thread_id => constant6_op_net,
      dbg_dw64counter => vdif_packetizer_v15_2_dbg_dw64counter_net,
      dbg_fifo_empty => vdif_packetizer_v15_2_dbg_fifo_empty_net,
      tx_data => data_x0,
      tx_discard => vdif_packetizer_v15_2_tx_discard_net,
      tx_end_of_frame => vdif_packetizer_v15_2_tx_end_of_frame_net,
      tx_valid => vdif_packetizer_v15_2_tx_valid_net
    );

  vdif_packetizer_v15_x0: entity work.vdif_packetizer_v15
    generic map (
      frameCountLimit => 67108864,
      frameLenLimit => 4096
    )
    port map (
      bitspersample => simulation_multiplexer4_dout_net_x0,
      ce => ce_1_sg_x10,
      clk => clk_1_sg_x10,
      complex => constant1_op_net,
      data_in => bitreducer8to2_v10_1_samples_net,
      data_valid => bitreducer8to2_v10_1_valid_out_net,
      dw64_per_frame => sl_10lsb_y_net,
      enable => constant4_op_net,
      epoch => constant8_op_net,
      epseconds => lsb1_y_net,
      log2channels => simulation_multiplexer5_dout_net_x0,
      rst => dly9_q_net,
      station_id => simulation_multiplexer3_dout_net_x0,
      thread_id => constant3_op_net,
      dbg_dw64counter => vdif_packetizer_v15_dbg_dw64counter_net,
      dbg_fifo_empty => vdif_packetizer_v15_dbg_fifo_empty_net,
      tx_data => data,
      tx_discard => vdif_packetizer_v15_tx_discard_net,
      tx_end_of_frame => vdif_packetizer_v15_tx_end_of_frame_net,
      tx_valid => vdif_packetizer_v15_tx_valid_net
    );

end structural;
